Synthesis Flow Overview

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Introduction:

Synthesis is a process of converting RTL (synthesizable Verilog code) into a technology specific Gate level netlist which includes nets, sequential cells, combinational cells and their connectivity. In other words, It is a process of combining pre-existing elements to form something new. It is the conversion of an idea into an implementation.

Logic Synthesis is combining primitive logic functions to form a design netlist that meets functional and design goals.

Synthesis Inputs:

Steps:

Translation: This is the first step of the logical synthesis. In this step, RTL is converted to a general (G-Tech) library netlist. During this step, more emphasis is on whether the intended logic is maintained or it gets changed.

Operations performed in this step:

1. Conversion of HDL into functional Boolean equivalent.
2. HDL syntax checking
3. Optimizes HDL
4. Arithmetic, Sequential and Combinational function mapping

Mapping: In this step, tool will map the (G-Tech) generic Boolean netlist into the gates available in the standard cell library. Boolean functions are mapped to technology specific primitive functions.

Optimization: In this step, tool modifies the mapping to meet the design goals in the following priority order by default.
Optimization step is constraint-driven. User needs to provide good constraints for effective optimization results. Optimal design is found as a result of synthesis based on the priorities set by the designer. The tool choose the combination of library cells that best meet the functional, timing, area and power requirements of the design.

Constraints:

-The design goal (timing, area, power) is defined by the constraints. Constraints are set of rules that set limits on circuit parameters according to parameter priorities and requirements.
-During synthesis process, every time there is a choice between several circuit variants, the one meeting constraints is chosen.

Synthesis Outputs: