Backend (Physical Design) Interview Questions and Answers

Physical Design Q&A

Q51. What is GDSII file?

GDS (Graphic Data Stream) is a file that was developed by calma company in the year 1971 and the GDS II in the year 1978.
It is a binary file format that represents layout data in a hierarchical format.
Data such as labels, shapes, layer information and other 2D and 3D layout geometric data.
This file is then provided to the fabrication plant that uses this file to etch the chip based on the parameters provided in the file.

Q52. What is a SDF file related to VLSI Physical Design?

SDF stands for Standard delay format.
It gives information on the timing data extensively used in backend VLSI design flows.
SDF gives information about

Path delays
Interconnect delays
Timing constraints
Tech parameters affecting delays
Cell delays.

SDF file is also used in the back annotation of delays in the gate level simulations for mimicking the exact Si behavior.

Q53. What is DEF file in VLSI?

The Design Exchange File, is an industry standard file that is used for representing logic and connectivity of an IC in ASCII format.
It generally defines die size, connectivity, pin placement and power domain information.

Q54. Explain the types of metal programmable ECO cells?

There are 2 types of programmable ECO cells, one is ECO filler and other is functional ECO cells. The ECO filler cells are constructed based upon the base layers known as Front-end-of-line(FOEL), FEOL are implant, diffusion, and poly layers. This allows any functional ECO to be performed using back-end-of-line layers.
Functional programmable ECO cells include a wide Variety of combinational and sequential cells with multiple drive strengths realized by using width multiples for filler cells. Their cell has the same FEOL footprint as that of ECO filler cells.
The only difference is that the functional ECO will use ECO filler FEOL layout and have contact connections to poly-layers and diffusion and metal1 layers for internal connections in order to construct a functional gate.

Q55. What is +ve unateness, -ve unateness & non-unate?

+ve Unateness: A timing arc is said by +ve unate, if output signal direction is same as the input signal direction or output signal does not change: Examples - AND, OR
-ve Unateness: A timing arc is said to be -ve unate, if output signal direction is opposite to that of input signal direction or output signal does not change Examples: NOR, NAND, Inverter.
Non-Unate: In a non-unate timing arc, the output transition cannot be determined solely from the direction of change of an input but also depends upon the state of the other inputs. Example: XOR

Q56. Can we get 0 skew what is the problem?

If skew is 0, then all the flops will trigger at the same time. So power consumption will be more.

Q57. what's the impact on the timing if you insert inverter on the capture clock pin?

Before inserting inverter, they have full clock cycle available for Setup.

Q58. Difference between clock skew and clock latency?

Clock skew is the clock reaching the clocked elements and different time.
clock latency is the clock reaching the clock input pin from where it is getting generated. From that pin only the clock will be supplied to different flops.

Q59. What is Pad limited design and core limited design. Is there any difference in approaches to handle these?

Pad limited design:

The Area of pad limits the size of die. No of IO pads may be lager. If die area is a constraint, we can go for staggered IO Pads. Core limited design:

The Area of core limits the size of die. No of IO pads may be lesser. In these designs in line IOs can be used

Q60. How will we decide chip core area?

Die Size = Core Size + IO to Core Clearance + Area of Pad (Including IO Pitch Area) + Area of Bond longest Pad

I/O-core clearances is the space from the core boundary to the inner side of I/O pads(Design Boundary)