Q491. What is wire load model (WLM)?
It is an estimation of delay based on area and fan-out.The delay depend on..
- Resistance.
- Capacitance.
- Area of the nets.
Q492. How a positive or negative edge triggered flip flop will effect the setup and hold violations?
Positive edge triggered flip flop will favour to setup (setup violations will reduce).Negative edge triggered flip flop will favour to hold (hold violations will reduce).
Q493. If we increase the fan-out of the cell how it will effects delay?
Fan-out lead to increased capacitive load on the driving gate.Therefore longer propagation delay.
Q494. What is multi driven nets?
It can be created in RTL by introducing drivers of same or different signal strengths.However during a net with multiple signals are not considered as a good practice.This could lead to failure in a post silicon verification as the driver strength can potentially get heavily altered during manufacturing defects.Many EDA tools don't allow multi driven nets in the design and the designers are expected to remove all multi driven nets from the design.
Q495. What is magnetic placement?
To improve the timing for the design or to improve the congestion for a complex floor plan we can use magnetic placement to specify fixed objects as magnets and icc moves their connected standard cells close to them.For the best results perform the magnetic placement before standard cells are placed.
Q.496. What are the types of checks done in prime time?
- Timing (setup,hold,transition).
- Design constraints.
- Nets.
- Noise.
- Clock skew.
Q.497. For Creating proper MMMC view definitions what information is required ?
Craeting proper MMMC view definitions requires the following information:
- Define RC(resistance and capacitance) corners (e.g, Worst and best).
- Define a library set to include all timing libraries that is used by the design(e.g, slow or fast libraries).
- Define delay corners for cell delay(data and clock) and net delay(data and clock).
- Define Constraint mode for each desiign constraint for all design function (e.g, setup and hold) and test (e.g, scan capture and scan shift).
- Define analysis views for each constraint mode and delay corner.
- Define analysis views set for setup and hold for all design functions.
The following are examples of MMMC View definitions:
Q.498. Difference between DRV(Design Rule Violations) and DRC(Design rule check) ?
DRV(Design Rule Violations) and DRC(Design rule check) are the terms used judge the quality of chip in different stages in VLSI Physical Design.
DRC:
It is actually used for making sure layout of a design must be in accordance with a set of predefined technology rules given by the foundry for manufacturability.
Stage checked at: Every stage after placement. Mainly the number should be low post route stage.
The main DRCs include shorts, opens, spacing between metals, n and p wells, same and different nets, min length, area and enclosure etc.
DRV:
The DRV holds a higher priority to DRC at any given stage of VLSI PD flow.
DRV is basically the set of factors based on which the design is characterized. All the standard cell/ macro/ any physical only cell library characterization/ selection is done with DRV kept in mind.
Main DRV are max_transition, max_capacitance, max_fanout. These generally characterize the input speed/slew, output load, driving capacity, routing, congestion and many other factors which affect the quality of the design.
Stages checked: Every stage and have to be solved if exceeding the specified target.
Q.499. what is the role of ERC in vlsi?
ERC stands for Electrical Rule Check and is run to check the connections that are considered fatal or dangerous ,
Some of the connections that could be dangerous include -
- If we short the output,
- If any input is left unconnected,
- If any gates are connected directly to supplies,
- If the design includes any possible ESD damage, etc.
Q.500. what happens if Assign statements are present in Synthesized netlist ?
Assign statement only specifies the function, it does not specify any gate or net. so it will create issue at implementation side. like at layout, how do you specify it in your spice netlist if no nets are defined.
