Q481. Expain Clock Jitter and its sources ?
Clock jitter is the clock edge inaccuracy introduced by the clock signal generation circuitry w.r.t ideal clock. Clock jitter may be viewed
as a statistical variation of the clock period or duty cycle.
Sources of clock jitter:
- Temporal power supply variations
1. Changing activity can alter supply voltage in different cycles affecting either the global or regional (local) clock
buffers.
- PLL Jitter
1. Supply variation at PLL can affect oscillator frequency.
2. PLL components do not have zero response time.
3. Reference clock jitter being multiplied by the PLL.
4. Global clock distribution may add jitter to PLL due to supply noise causing the feedback clock signal to seem to jitter.
- Wire coupling
1. Changing data can alter coupling in different cycles
- Dynamic De Skewing Circuitry
Q482. What are the advantages of NDR's?
- By applying the double width we can avoid the EM.
- By applying double spacing we can avoid the cross-talk.
- Help's to avoid congestion at lower metal layer.
- Help's pin accessibility of std-cells .
Q483. What is the concept of rows in the floor plan?
The std-cells in the design are placed in rows.All rows have equal height and spacing.The width of the row can vary.The std-cell in the row get the power and ground connection from vdd and vss rails.Sometimes technology allows the rows to be flip.So they can share the power and ground rails in vdd-vss-vdd patron.
Q484. What is temperature inversion?
At higher CMOS technologies cell delay increases when temperature increases.But when you are in lower technologies i.e below 65nm cell delay has inversely proportional to temperature.
Q485. How can you reduce dynamic power?
- Reduce power supply voltage.
- Reduce voltage swing in all nodes.
- Reduce the switching probability (transition factor).
- Reduce load capacitance.
Q.486. Why double via insertion?
To reduce the yield loss due to via failures,double via's are inserted traditionally double via's where inserted in post route and then modify the routing to fix any DRC's.
Q.487. What is metal fill insertion?
At the time of etching they use some type of chemicals due to that chemical metal loss will be more for that reaction we are inserting the metal fills.
Q.488. What is metal slotting?
It is the Technic for avoiding the problems like metal lift off and metal erosion.
Q.489. What is dishing effect?
It is defined as the difference between the height of the oxide in the spaces and that of the metal in the trenches.It is caused by CMP.It may reduced by some dummy fill Technics effectively.
Q.490. What are the violations solved in LVS?
- Shorts.
- Opens.
- Missing text layers.
- Missing lib in GDS.
- Missing soft layers.
