The synchronizer is used to avoid metastability. It is a digital circuit which is used to convert asynchronous or signals from different clock domains into the receiver’s clock domain so that capturing would not cause any metastability issue. It provides sufficient time for the clock signal to settle down the metastable output in the receiver’s clock domain.

When the two D lathes are connected back to back (as shown in Figure), it forms a flip-flop.

Here, one latch acts as a master flip-flop, other acts as slave flip-flop. As we know that latch is level sensitive and a flip-flop is an edge-sensitive device. The first latch is low level and the second latch is high level. It forms a rising edge sensitive D flip-flop. Latch consumes less power than a flip-flop. There are chances of glitches in latch is more than flip-flop.

The speed of the device is directly proportional to the following parameters:

1. Width of the device
2. Clock slew rate
3. Load capacitance

The application of probability distribution in determining possible circuit outcomes, for variation in the gate and interconnect timings is known as statistical STA. It is different from conventional/deterministic/traditional STA in the following ways:

1. In statistical STA, there is no chance of miss paths, as it does not have any vectors.
2. It can be used for circuit optimization.
3. The run time is linear.
4. It cannot handle spatial correlation within the die, which is possible in the case of deterministic STA.
5. There are correlational problems while using statistical STA, it needs more corners to resolve design issues.

1. Cadence Encounter
2. Synopsys Primetime
3. Altera Quartus II
4. IBM Eins Timer

Static Timing Analysis is used to check mainly the setup and hold time checks. But it also checks for the assumptions made during timing analysis to be holding true. Mainly it checks for cells to be within the library characterization range for input slope, output load capacitance. It also checks for integrity of clock signal and clock waveform to guarantee the assumptions made regarding the clock waveforms. A partial list of things it checks is here :

1. Setup Timing
2. Hold timing
3. Removal and Recovery Timing on resets
4. Clock gating checks
5. Min max transition times
6. Min/max fanout
7. Max capacitance
8. Max/min timing between two points on a segment of timing path.
9. Latch Time Borrowing
10. Clock pulse width requirements

No you can not sign off the design if you have hold violations. Because hold violations are functional failures. Setup violations are frequency dependent. You can reduce frequency and prevent setup failures. Hold violations stemming from the same clock edge race, are frequency independent and are functional failures because you can end up capturing unintended data, thus putting your state machine in an unknown state.

The purpose of clock gating is to block the clock pulses and prevent clock toggling. An enable signal either masks or unmasks the clock pulses with the help of an AND gate. As it is clock signal which is in consideration here, care has to be taken such that we do not change the shape of the clock pulse that we are passing through and we don’t introduce any glitches in the clock pulse that we are passing through.


As you can see in the figure the enable signal has to setup in advance of the rising edge of the clock in such a way that it doesn’t chop the rising edge of the clock. This is called the clock gating setup or clock gating default max check. Similarly the tuning off or going away edge of the enable(EN) signal has to happen well past the turning off or going away edge of the clock, again to make sure it doesn’t get chopped off. This is called the clock gating hold or clock gating default min check

Worst max margin will decide the max frequency a design will work on. As setup failure is frequency dependent. Hold failure is not frequency dependent hence it is not factored into the frequency calculation.

Setup failure is frequency dependent. If certain path fails setup requirement, you can reduce frequency and eventually setup will pass. This is because when you reduce frequency you provide more time for the flop/latch input data to meet setup. Hence we call setup failure a frequency dependent failure. While hold failure is not frequency dependent. Hold failure is functional failure.