As multiple vias are introduced, the resistances will be in parallel, which will reduce the RC delay and further decrease the crosstalk accordingly.

If two signals are close enough, they can cause crosstalk due to coupling capacitance.

Crosstalk delay:
When the one net is switching at a faster rate and the other is switching at a slower speed, due to crosstalk, the speedy net will boost-up the slower net. This is known as crosstalk delay, which is due to timing errors of signals.

Crosstalk noise:
In the case of crosstalk noise, one net is idle (either at logic 1 or logic 0) and the other net is in transition mode (switching from 0 to 1 or vice versa). There may be the introduction of unwanted signal transition due to the coupling capacitor. The reason for crosstalk noise is charge storage effect, power supply or substrate noise. The crosstalk noise analysis tool determines the worst-case glitch on the idle net. The commands for noise analysis are report_noise, check_noise, and update_noise.

All devices along a chip should run at a specific speed and interconnects should be either at the worst-case or best-case corner. But due to some variations at the manufacturing level, the speed is not uniform throughout the chip. There is variation in effective channel length and width of transistors. Due to complexities and variations in submicron technologies, the devices with the same size may have different width as compared to the idle condition.

The major on-chip variations are:

1. Variation in the channel length
2. Variation in temperature
3. IR drop variation
4. Variation in transistor width
5. Variation in threshold voltage
6. Variation in interconnects

1. Etching
2. Photolithography
3. Chemical mechanical planarization

A clock is a signal that oscillates between low to a high state and vice versa. A network that distributes clock to all clocked elements, for example, buffer and metal network, is known as clock distributor. Whereas, the clock generator is an electronic circuit that produces timing signals. The clock generator is used in the synchronization of a circuit. The basic components of the clock generator are the amplifier and resonant circuit.

The performance difference between the die is known as global chip-tochip variation. It is modeled as operating corners. Within the same die, if there is a performance difference between the transistors, it is known as local on-chip variations. It is modeled as an added derating factor to skew calculations.
The variation constraints may be:

1. The thickness of the oxide layer
2. Transistor channel dimensions (length and width)
3. The number of doping atoms

There are two clock distribution systems:

1. Clock tree, also known as Clock Tree Synthesis (CTS). It is placing and routing clock tree elements.
2. Clock mesh or Clock grid distribution system

The main goal of the clock grid distribution system is to provide uniform delay from the source of the clock to the end receiver i.e. flip-flop, latches, etc. It minimizes the clock skew by providing the concept of stages. The number of stages is dependent on the size of the chip or process technology. It is desirable to have a minimum number of stages. The clock distribution system targets to have the same delay in all stages.

There are two distribution stages; one stage is from the clock source to the boundaries of the block and another stage is a distribution from block boundaries to block. The clock grid distribution system is shown as in Figure.

In stage two, the clock distribution is done inside the block through a fixed number of stages through the mesh/grid of clock buffers. The clock buffers should be symmetric.

In the clock mesh distribution system, the main clock signal is divided into parallel paths using drivers. The array of buffers is cross-connected in a metallic mesh. The driver feeds these buffers. It routes the path to clock sinks. A resonant structure is created using mesh cross-links. The delay of buffers is terminated because of the resonant structure. The clock mesh distribution system is shown in Figure


This kind of clock distribution system is used in high-speed microprocessors. Usually, clock routes are shielded to reduce the coupling effect and variations due to coupling. Due to the variation tolerance nature of the clock mesh system, the problem of clock skew is reduced to a great extent.

In the clock tree distribution system, the clock is distributed to all receivers i.e. flip-flop, counter, etc. In clock tree synthesis, the number of stages is optimal. It is not necessary to have an equal number of stages throughout the distribution system. As the number of stages is less, so the power dissipation is also low. The clock tree distribution system is shown in Figure.


For slow clock designs, the clock tree distribution is best suited