Generally, it was expected to complete the launching of data and capturing the same within one clock cycle. But there may be the scenario, where it needs more than one clock cycle to complete the launch and capture process. It can be accomplished by instruction:

Set_multi_cycle_n -from < start point> -to

Here ‘n’ specifies the number of clock cycles needs to complete the launch and capture task. This has been instructed to timing tool to verify and analyze the timing path constraints specifications and violations.

A wire connecting pins of standard cells is known as the net. The timing delay between input and output pin of a cell is known as cell delay and the timing interconnect delay between the driver pin and load pin is known as a net delay. The stage delay is the sum of net delay and cell delay.
The net delay is the time needed to charge or discharge all the parasitic of the net i.e. resistive, capacitive, inductance, etc.
If the physical wire is not present, we cannot estimate the net delay. Because the accurate value of parasitic depends on the dimensions of the wire.

The net delay or cell delay depends on the following parameters:

1. Input skew
2. Library setup time
3. Library delay model
4. Cell load characteristics
5. Cell drive characteristics
6. Operating conditions
7. Back annotated delay
8. Wire load model
9. External delay

Every logic gate and net have min and max delay. In static timing analysis, the maximum delay is known as the worst delay and the minimum delay is known as the best delay. The rise and fall delay are also categorized as min and max delay

1. Wire load model
2. Elmore delay model
3. Lumped capacitor model
4. Lumped RC model
5. Distributed RC model
6. RLC model
7. Transmission line model

In design, if a particular delay model is applied, then the same model applies to all cells in a particular library. In a single library, multiple delay models cannot be applied.

A path is the static sensitized path when all the side inputs of the path hold non-controlling values. The controlling (non-controlling) value for the AND gate is 0(1). The static sensitization is sufficient for a path to be a true path in the circuit.

A path is statically co-sensitized if the input corresponding to the path is consistent with the value at the output of each gate on the path.
In a co-sensitized path, if path input is controlling then side inputs can also be sensitizing.

A set of design issues such as crosstalk, cross-coupling effect, electromigration, and IR drop is called signal integrity issue. A small variation on the single die can violate the design of the whole chip. In an integrated circuit, a wire is routed to another wire using some insulator. An increase in signal value of one wire may vary the signal value of another interconnected wire, in this way, the signal will lose its integrity.

Due to the cross-coupling of the capacitor, the signal at one net/wire can interfere with the signal on neighboring net/wire. This disruption of the signal is known as crosstalk. This may further violate set up and hold time violation. The crosstalk creates undesirable voltage spikes known as glitches. There is a possibility of functionality errors due to glitches and timing errors due to deviation in signal timings.

When the spacing between the two conductors is more, the width is increased. The cross-coupling will be reduced and consequently, the crosstalk will be reduced.