The clock skew can cause two types of violation:
(a) Setup violation
(b) Hold time violation

When the clock signal travels at a slower speed than required, then the integrity and synchronization between source and destination are destroyed. The previous data is not stored for sufficient time to be clocked through properly, it is known as hold time violation.

When the clock signal travels faster, the destination receives the clock tick before the source, it causes set up the violation. As the data reaches late as well as it is not stable before the clock signal, it leads to setup violation.

When the clock edge deviates from its ideal position, it is known as clock jitter. The reason for clock jitter may be noise, power supply variation or interference due to neighborhood circuits. The clock jitter is shown in Figure



The jitter may affect the clock signal to be slower or faster that will further violate the setup or hold time constraints. This will degrade the performance or functionality of the chip or circuit. So, it is an important parameter while designing the circuit and timing analysis.

There are four types of clock jitter, which may be present in the circuitry.

1. Period jitter The average value of clock period is the deviation over the RMS value of the deviation of 10,000 clock cycles. It is also known as the peak-to-peak period jitter.

2. Cycle to cycle jitter
Within a random 1000 clock cycles, the deviation between two adjacent clock cycle edges is known as cycle to cycle jitter. It measures the difference between minimum clock edge change to the maximum clock edge change.

3. Phase jitter
This is rapid and short-term fluctuations due to phase noise in the frequency domain. It can be translated into jitter values.

Phase noise = signal power/noise power , normalized at 1Hz bandwidth at a given offset from the carrier signal.

4. Time interval error (TIE) jitter:
It determines how far each active edge varies from the corresponding edge of the ideal clock. The RMS TIE measures the standard deviation of timing error.

Cycle to cycle jitter is used for determining high-frequency jitter. In the random group of clock cycles, it represents the peak value of the clock jitter.

The reset is the parameter to make the circuit initialize. As hardware has not self-initialization property, so, reset forces it to a known state. During the simulation, reset takes the circuit to the starting and in real hardware, the reset powers up the circuit. There are two types of reset:

1. Synchronous reset
2. Asynchronous reset

The synchronous reset means it is sampled with the clock. The synchronous reset will not be activated until the clock edge is high. The reset should be stretched so that it is visible during the clock signal.
Advantages:

1. A complete synchronous circuit is achieved.
2. The problem of clock glitches is reduced.
3. Deassertion will happen within 1 clock, so it will meet the reset recovery time constraints.

Disadvantages:

1. It is not suited for clock gated circuits.
2. It makes the process slow.
3. A clock signal must be present always.
4. The reset signal should be wide enough to be visible through the clock signal.
5. Reset signals may interfere with other signals during timing analysis and synthesis.

The synchronous reset will be used when a designer needs a complete synchronous circuit, which has no metastability or clock glitch issues.

An asynchronous reset will be activated as soon as the reset signal is high/enabled. It is not dependent on the clock signal. There is no need to wait for the clock signal.
Advantages:

1. No need to wait/activate the clock signal.
2. It makes the process faster.
3. Reset has the highest priority.

Disadvantages:

1. Metastability may occur.
2. Chances of clock glitches may occur.

The asynchronous reset will be used when the chip needs to be powered up before the clock signal.

Reset Assertion: Activate/apply the reset i.e. when the reset signal is logically true.
Reset De-assertion: The release/disable of reset i.e. when the reset signal is logically false.
During asynchronous reset, the de-assertion may cause metastability because it may be the case that some flip-flops come out of reset before others.
During an asynchronous reset, the reset assertion and de-assertion should meet the minimum required pulse width.

Reset recovery time is timing validation rule for clock and reset signal. It is similar to the setup time rule. Reset recovery time is the time between de-assertion of reset and activation of the next clock edge. The recovery timing check ensures the same i.e. as soon as asynchronous reset becomes disable or de-assert, the check should ensure that there will be sufficient time to recover so that the next clock will be effective.

When reset is released, some time is taken to make it stable. So, reset recovery time is the minimum time required between the release of reset and arrival of the next clock edge.

For example, let us take a case of a flip-flop, if the clock edge becomes active immediately after the removal of reset, it will take the flip-flop into an unknown state, which will violate the timing constraints. The Figure 1.7 shows reset recovery time.

Reset removal time is timing validation rule for clock and reset signal. It is similar to hold time rules. The reset removal time depicts the minimum amount of time between the clock edge and the release of the reset signal.
So, reset removal time is the minimum time required between the arrival of the clock edge and de-assertion of reset.

It should be taken care that the de-asserted reset signal should not get captured on the clock edge at which it is launched. After the clock edge, the reset signal must be stable for some time i.e. removal time. The reset removal time is shown in Figure.