The setup time violation is frequency-dependent. It can be removed or reduced by changing the frequency of the clock. Whereas the hold time violation is the functional failure of design. It is frequency independent. It cannot be repaired by slowing down the frequency of the clock, as it introduces data race. So, with a change in the clock period, the design with setup time violation can be used but the hold time violation persists in the design.

Time Borrowing is the concept of borrowing the time from the next clock cycle. It occurs in the case of the latch. It is also known as cycle stealing. It reduces the data time to arrive at the next clock cycle or in another case, it permits the design to use slack from the previous clock cycle



This example will clear the concept of time borrowing from the next cycle and slack from the previous clock cycle, as shown in Figure.

Assume that there is communication between two flip-flops, where the clock period is 5 ns. Path 1 has a timing delay of 6 ns. The timing can be met, if the clock period becomes 6 ns, otherwise there will be timing violation in path 1. But as the clock period will increase, it may degrade the pipelineperformance. This problem is resolved with the replacement of flip-flop 1 by a latch, because the edge-triggered flip-flop changes the state an edge transition, whereas latch changes state as long as the clock pin is enabled. The latch opens at the same time as flip-flop i.e. 0ns, but it closes at 2.5 ns (negative edge of the clock). So, path 1 has an extra 2.5 ns to borrow from the next cycle. The time borrowed by path 1 = 6ns-5ns = 1 ns, whereas it can use 2.5ns, so it has a positive slack of 1.5 ns. In such a scenario, there will be no time violation by path 1. Path 2 will start immediately after path 1. Path 2 will add a 1ns delay.

Path 2 could use up to 4 ns (2.5 ns is half period of clock cycle + 1.5 ns positive slack), but it uses only 1 ns. The data capturing of flip-flop 2 is available at 4 ns. The flip-flop’s rising edge occurs at 5 ns. So, a positive slack is of 1 ns.

Time stealing is the concept of adjusting the clock phase at flip-flop2 so that data arrival time at the capture edge of flip-flop2 will not violate the timing constraints. Time stealing is used when specific logic partition needs additional time which should be deterministic at the start time.

1. Time borrowing can be multistage.
2. In time borrowing, both data launching and capturing should be completed using the same phase of the same clock. If the launching and capturing are out of phase, time borrowing will be deactivated.
3. It should be held in the same clock cycle.
4. Time borrowing slowdowns the data arrival time.
5. Time borrowing affects setup slack calculation.
6. Hold slack calculation is not affected with time borrowing because the fastest data is used by hold time.

1. Time borrowing applies to latch-based design whereas the time stealing applies to flip-flop-based design.
2. The method of borrowing time from the shorter paths of the next design stages to the bigger path is known as time borrowing. The adjustment of the clock cycle for flip-flop2 as per the data arrival time is known as time stealing.
3. In the time borrowing concept, there is no interference with the clock phase. The latch uses the previous cycle slack automatically through the pipeline. Whereas time stealing, steals the time from the next stage and it results in less time to the next stage. The designer will take care that the next stage delay should be lesser than the difference between the clock period and phase shift.

The negative time borrow can be calculated as the difference between data arrival time and clock edge.

Negative borrow time = Arrival time-clock edge
The negative borrow time states that there is no borrowing takes place.

Maximum borrow time = clock pulse width-library setup time
Along with library time at end of latch, clock latency is also subtracted from the clock pulse width to achieve the maximum borrow time.

The slack is the factor that determines the speed or frequency of the specific design. It is related to the timing path and can be calculated as:
Slack = Actual time-desired time

The negative slack means, there is some timing violation. The design has not achieved a specific speed or frequency.
The positive slack means, the design is achieving the specific speed or frequency. It has some extra margin as well.
The zero slack signifies that there is no margin, but the designer is already working on the exact speed or frequency.

The basic static timing equations are as follow:
Clock period > T cq + T pd + T su ......(1.1)
Where Tcq is the maximum time from clock to output; Tpd is maximum propagation delay time through the logic and Tsu is maximum setup time. Hold time < Tmin (R) + Tmin (logic) ......(1.2)
Where Tmin (R) and Tmin (logic) are the minimum delays by register and logic respectively.

Clock period + clock skew > T cq + T pd + Tmin (logic) ......(1.3)
Where clock skew is a spatial delay of the clock.

Hold time + clcok skew < T cq + T pd + Tmin (logic) ......(1.4)
Clock period − jitter (worst case) > T cq + T pd + T su ......(1.5)
Hold time + jitter (worst case) < Tmin(R) + Tmin(logic) ......(1.6)
The worst case of jitter is the situation where the rising edge is late and falling edge is early.

Worst case jitter = 2 × jitter ......(1.7)
So, the maximum frequency of operation (1/clock period) is dependent on the maximum Tcq, Tpd, and Tsu. The setup violation can be fixed by varying clock frequency and temperature. The temperature will further reduce the threshold voltage and makes the device faster. The hold time violation cannot be fixed by changing the clock frequency.

In synchronous circuits, if the clock signal arrives at different components at different times, although the clock signal is generated from the same source. The reasons for clock skew may be temperature variation, capacitor decoupling, wire interconnect length or material imperfection.

When the transmitting source receives the clock tick before the receiver, it is known as the positive clock skew. The positive clock skew enhances the operating frequency and makes the hold time tougher.

When the transmitting source receives the clock tick after the receiver receives it, this is known as the negative clock skew. The negative skew decreases operating frequency.

When there is synchronization between transmitter and receiver for clock arrival, it is known as zero cock skew.
Clock skew is also known as clock uncertainty.