For static timing analysis, various timing path and path delay is analyzed. The gate delays and net delays are used to calculate path delays. In the timing path, the data is launched (start point) and pass-through using combinational components and as soon as it meets with any sequential component (endpoint), it stops. If at both endpoints, there are sequential elements that are triggered by an asynchronous circuit i.e. using two different clocks, then for setup and hold time analysis, the LCM of both clock periods is considered. The launch and captured edge can be explored using LCM of the clock pulse.

In synchronous circuits, the timing path starts at the clock pin of Flip-flop A. The delay introduced from the clock edge to data output is known as the first stage of delay. The data goes through a series of combinational elements and interconnect wires. Each stage has a timing delay. When data reaches to another Flip-flop B, timing path stops. The clock divergence point is generated because the same clock is used to generate data through Flipflop A and sample data through Flip-flop B. The Stages of timing delay is represented in Figure.

Following timing paths are majorly considered:

1. Clock pin of one register to D-pin of another register.
2. Input to D-pin of register.
3. D-pin of the register to output.
4. Input to output through combinational elements.
5. Input to the macro input pin, macro input to the macro output pin, macro output to the primary output pin.

The data needs to be settled before the capture edge of the clock activates. If the data does not settle before the capture edge, the flip-flop will enter into the metastability state. The time taken by input data to be stable before the capture edge of the clock is known as setup time.

When the capture edge of the clock is deactivated, the time for how long the data remains stable is known as hold time of flip-flop.

The set-up time and hold time are calculated by the input data slope, clock slope, and output load.

At the active edge of the clock, when the data is launched and transverse through flip-flop A and reaches output pin of flip-flop A with some delay. The data should be stable before the capture edge. But sometimes delay makes the circuit unstable and flip-flop enters into metastability and does not satisfy the set-up timing requirements. A similar condition is withheld time, thereafter the assertion of clock capture edge, the data becomes unstable, which violates the hold time requirement of flip-flop/sequential element. The hold time violations are functional failures.<

1. High clock slope
2. Very fast transition from the output of flip-flop A to the input of flip-flop B.
3. Sharp clock skew rate due to which second clock edge delays by a first clock edge. There is no synchronization in the alignment of two clock edges.
4. Capacitance coupling
5. Design issues

The static timing analysis tool is the exhaustive analysis tool that explores and analyses all the timing paths, even if it does not happen.

In timing analysis, the critical path is considered that timing-sensitive functional path which introduces the longest delay in the design. The timing path from the clock to the output of the first flip-flop may have some delay. Assuming both flip-flops are having the same clock if the delay (Clk-output of flip-flop A) is less than the clock period, it is known as timing requirement meets otherwise the timing requirement violates. The path with the highest delay is known as the critical path.

When no data is transferred from start to endpoint, this path is known as a false path. This is a functionally incorrect path. This path is intentionally inserted by the designer to develop a relation between asynchronous circuits. For example, in design, two D flip-flops are not enabled at the same time.

When the generation of data, transfer data, and computation of data takes place in more than one clock cycle, i.e. the data takes more than one cycle to travel from the start point to endpoint, is known as a multi cycling path.

In between the start point and the endpoint, there are many types of ‘path’. The path which has the minimum delay is known as an early path, best path or minimum path i.e. through this path, the data takes minimum time to reach the endpoint. The path which is having the largest delay is known as the worst path, late path or maximum path, i.e. using this path, the data takes maximum time to reach the endpoint.