Physical Design Question & Answers | Q&A |Physical Design| VLSI Back-End Adventure

Physical Design Q&A

Q391. Why timing analysis is an important factor?

Timing analysis is used to select appropriate components, as few components are slow. The performance of the circuit degrades because the slow component introduces wait for the state. The fast component is costly. So, timing analysis selects the appropriate component as per the specific application.
Timing analysis verifies whether the circuit is properly designed and work with reliable output for all combinations of input.

Q392. How many types of timing analysis are done in VLSI?

Timing analysis is of two types:

STA: Static Timing Analysis: checks static delay requirement of circuit. It does not require any input or output variables.
DTA: Dynamic Timing Analysis: The function of DTA is to verify the design functionality with the help of input and output variables.

Q393. What are the important features of STA?

No need for input-output variables.
Simple to use STA tools.
The input to STA is a library, netlist, constraints, and parasitic (R & C), all are commonly available.
STA uses device models based on lookup tables or constant I/V models. It uses the Elmore wire delay model.
STA performs worst-case analysis to check delay requirements of the circuit. It performs timing analysis on all possible paths i.e. it includes potential false paths also.
It is efficient for only a fully synchronous design.

So, the conclusion is:
• STA breaks the design into different timing paths.
• Calculate the signal propagation delay along each path.
• Check violation of timing constraints inside design and me/O interface

Q394. During timing analysis, what are the ideal characteristics of a clock?

The clock should be free of glitches.
The period of the clock should be properly defined and proper phase relationships should be established between two different clocks of interest.
The clock must meet pulse width requirements.
The Jitter parameter needs to be taken care of when the clock speeds increase. For example, PLL should have maximum jitter.
When data is transferred from one clock edge to another, the worst-case duty cycle should be used.

Q395. What are the major functions of STA?

STA checks the following parameters:

Setup time
Hold time
Reset removal and reset recovery time
Clock gating
Min/max fan-out range
Maximum capacitance range
Clock pulse width requirements

Q.396. Which input files are required to run STA?

Gate level netlist
Parasitic files
Constraints
General setup scripts.

Q.397. When Static Timing Analysis is done?

STA can be done after synthesis. It should be done once before layout and 2–3 times after layout. The sign-off can be done after routing.

Q.398. How STA is different from circuit simulation?

As STA does not handle input-output variables so, it is faster than circuit simulation.
It provides deep insight by worst-case timing analysis of all possible logic conditions, whereas the circuit simulation verifies a particular set of input-output variables.

Q.399. How STA is performed on the circuit?

The circuit design is further bifurcated into a possible set of timing paths.
The signal propagation delay is calculated for all the paths.
STA tool analyses the timing constraint of all possible paths and compare with the ideal timing constraints and check whether there is any timing violation in the circuit.
It checks timing violations inside the design as well as at the input-output interface.

Design flow:
Simulation→Synthesis→STA→Layout→Sign-off