Q381. Two metal shapes we have in the design and one metal shape with 1X width and other metal shape of same layer with 2X width. What changes you can expect in delay of these two metal shapes?
As the width is inversely proportional to R, by increasing width R will reduce. And by increasing width, capacitance will increase Considering above basics, conclusion can be made as delay is dependent on RC product thus delay can be increase/decrease based on RC product
- length of shape (for small shapes, resistance impact is less compared to capacitance). For smaller shapes, delay will increase more compared to longer shape as with increasing width resistance also reduce making RC less increase.
- Looking at lower node perspective, at lower nodes like 7nm and below, cross layer coupling capacitance becomes dominant.
Q382. Out if the following two dbs, which one would you pick and why?
- with huge insertion delay and minimal skew.
- with less insertion delay and more skew.
Timing of the block is better in case 1.
Case 1.
Reason: depends on full chip timing and total cell utilization at optcts stage. If huge latency and minimum skew is there and timing of block is good but need so check fullchip timing with that case if it is also good with that latency and incremental utilization in optcts doesn’t have much difference as compared to case 2 then we can go with case 1 otherwise I will go with case 2.
If not convinced, then explain this:
let's say full chip two tile and one tile timing is comparable then we need to check what is the total utilization at optcts or u can say like what is the incremental utilization at cts stage means clock cell area if those are less we can go with less area option but first I will prefer to check fullchip timing one tile and two tile. Because I think if timing differences will be there then in eco stage anyway we will do skew or use ult to fix timing and that time anyway power will be more in that case. But if timing is meeting in that case then we can do vtswap to recover power I think. means I will prefer to choose timing first then I will go with power
Q383. What are the differences between 14nm and 7nm?
Going down means from higher to lower technology node we facing the more complex challenges like
- Crosstalk
- More DRCs
- more Ir drop
- more Area reduced more congestion issue.
- Signal Em violation
- more Power dissipation more
Q384. All the violations in the design are clean, except one transition violation. Can we tapeout our design?
We shall not tapout design until all logical drc and timing issues are met!!! The reason is as below:
(1) Transition violation affects the functionality, power budget as well as timing budget. let’s look into this briefly
i. Effect on functionality. Transition violation will impact on noise margin of the cell because cell load capacitance may fail to be charged till full VDD logic level during TLTH/THTL at input gate of the cell.
ii. Effect power budget Due to transition violation, cell pull-up and pull- down network will be ON simultaneously because of this, there will be a short circuit current/leakage current direct from VDD rail to VSS rail in design. Short circuit current will lead the short circuit power dissipation. So, we may fail to attain to achieve subsequent power budget given in spec throughout the design phase.
iii. Effect on performance/timing/speed/delay Transition violation will impact on rise and fall slew at the input to the cell, which will lead the timer engine to calculate cell delay from liberty file with extrapolation technique, which will add pessimism in our design unlike interpolation technique. As of extrapolation technique is not accurate, since there is no Gaussian curve/distribution relation for given MCMM scenario is define for outer boundary for cell delay calculation from a delay table in liberty file for a violated logical drcs. Still Statistical STA and Parametric STA method may add pessimism in a design for conducting extrapolation technique for a violated transition time.
Q385. In the picture attached, comment on possibility of antenna violation in each case, with reason.
(Given length of M3 alone as we are focusing on M3 antenna alone)
Case 1 have issues as it has jumper.
Case 2 and 3 will have issue.
as Antenna violation occurs when a longest single metal layer directly connected to gate terminal which can be seen in case 2,
whereas in case 3 (area of metal layer / area of gate) is less than allowable ratio Allowable ratio = allowable metal area/gate area So for third case is (25x5)/1=125 125 is greater than allowable metal area (ratio) therefore we will get antenna violation.
Q.386. What is the difference between 'giving mcp of 2 for setup in between flopA to flopB' and 'adding a register in between flopA and flopB'?
If same, do we have any complications involved in implementing latter case?
Difference in simple words,
- If a path had N number of MCP, we will get data once per ever N clock cycles
- If a path is pipelined (registered in between) with N registers, we will get data at every cycle but with a latency of N clock cycles.
And coming to the use cases, Taking MCP is easy compared to registering but it all depends on design data flow requirement to decide between MCP and registering.
Q.387. Two clocks(clka and clkb) generated outside the block from same master clock, those two clocks entered your block through ports and you have clock definitions on ports in your block.
- Will the PNR tool treat them as asynchronous clocks or synchronous clocks?
- If you want tool to treat them as synchronous, what would be constraint?
- If pll generated these two clocks freq/time period will be same. 2.
- In constraints both the clocks get generated from different ports. So, Tool sees them as different clocks until you give some balancing relation through sdc constraints (as they are synchronous)
- now the problem comes with balancing., if launch flop has clka as clock and capture flop has clkb as clock and datapath exists between two flops, the timing violations will be seen because the way balancing and clock building done.
- Need to specify balancing options between these two clocks even though period is same.
Q.388. Why clock gating is timing critical in the design?
clock gating cells generally have huge fanouts , which results in huge latencies from the clock gate output to the clock sinks . So this will cause timing failure for the enable pin for the clock gates as well timing violations on the path after the clock gate Output.
Q.389. why do we have different thickness for different metal layers? And why is that the thickness of the metal layer increases from bottom layer towards top and not the other way round? Why it can't be constant for all the metal layers?
For fabricating thick layers we need to have higher spacing between two adjacent metal lines.
Lower metal layer have less thickness so that the pitch can be reduced as less as possible. This is needed because lower metal layers have to connect to dense pins.
If the lower metal layers have higher thickness then pitch will also increase and due to higher pitch of M1, we cannot pack more standard cells in an area.
Q.390.What do you mean by STA?
STA refers to Static Timing Analysis. It is a technique that is used to verify the design of a circuit in terms of timing. It validates whether the design could operate at the rated clock frequency. STA further checks all possible ways of
timing violation.
