a. Things to be done in start of ECO PHASE:

i. Freeze all clock routes
ii. Fixed all critical cells
iii. Freeze all critical nets
iv. Set the ecomode settings:

1. Update timing: false; it is disable as optimization command are not run.
2. Legalize cells: false; use will call whenever required.
3. ecoRoute: false, user will call whenever required

b. Automated:

i. Eco flow
ii. Net correction or revert by DEF

c. Manual (verify 2 times):

i. Manually implementing the eco (connect-disconnect Or attachTermdetachTerm)
ii. Net correction with manual routes
iii. Remove power / ground and use these routing tracks for signal routes. Freeze all these manual routings (set_attribute / setAttribute), COVER (cadence) attribute on cells with will not allow to be modified by anyone.

a) Automatically (insert_buffer), manual (connect-disconnect)
b) TCL based buffer insertion by by-pass the buffer BUF1 from other path and use in required path (AND1/a)

Step 1: disconnect net connected to BUF1/a
Step 2: disconnect the pin from net connected to BUF1/z
Step 3: connect the net which was connected to BUF1/a to the pins which was driven by BUF1/z
Step 4: disconnect AND1/a from the connected net
Step 5: connect the net which was connected to AND1/a pin to BUF1/a pin
Step 6: connect the net of BUF1/z to AND1/a pin

a. By attribute
b. By NDR
c. Manual

a. Interactive mode of operation is the method where designer decide the fixes.
b. Tool optimize only up to the defined CONS or fixed time. Once these limits are reached and tool has not given the expected output, designer needs to fix these in interactive mode

a. Verilog change for any functionality

i. PORTS added
ii. Few gates connection modified
iii. Comes from designer (functionality addition, BUG)
iv. Time lines of the design and changes in DB
1. 2000 nets connection update: DB needs to be checks (implementation, STA)
2. 10 Flops added: adding additional timing paths, CTS network has to be build

b. STEP:

i. INPUTs: 3. MODIFIED PD Verilog netlist
4. PPT, EMAIL, NOTE

C. Generate the ECOs (functional eco) in TCL format for the PD tool

i. Using TCL, tool commands
1. ICC commands needs to be use
2. Compare the netlist and dump the changes in TCL
ii. Synth tool (DC from Synopsys) with optimization
1. Cells placement
2. Cells sizing

iii. User generate the ECO with tool commands
1. Assignment:
a. UPF changes for power assignment of the ports
b. Other changes required for multi-voltage domain

d. ISSUES:

iv. Verification
1. RTL->NETLIST->PD->FECO: Implementation
2. LEC, RTL <-> Synth (single bit, multi-bit)
3. CLP, same as LEC checks
4. LEC - PA, extra input CPF, UPF (IEEE-1801)
5. Multi-bit Synthesis (where single flops are combined to multi-bit flops)
v. After FECO, below stage modification required
1. RTL - manual effort
2. Synth - manual effort
3. PD - tool automated commands
4. STEP to generate the FECO for PD
vi. Target:
1. Generate the FECO
2. Implement the FECO
3. Validate STA, PV
4. LEC FECO netlist ↔ after implementation, GATE-GATE LEC check

e. Generate FECO:

i. Build logical data with current netlist ii. Compare this logical build DB with FECO modified netlist received iii. Write the changes in tool commands
1. Contains only logical changes

f. Implementation of FECO:

i. Make the logical design changes as per generated FECO
ii. Place additional cells added in FECO

1. SEQ cells added a. CTS needs to be build as per guidelines comes
2. Combinational cells added
3. Placement of these new cells (seq, combo) should be done as per timing
iii. DRV
iv. Timing vios
v. ECO-Route for the modified nets
vi. LEC, CLP GATE-level

a. Identify high toggle cells (clock nets: 200%, Signal nets based in VCD, TCF, SAIF)
b. More clock cells are clustered

a. Identify high toggle cells (clock nets: 200%, Signal nets based in VCD, TCF, SAIF)
b. More clock cells are clustered

a) Dummy metal FILL is adding extra coupling capacitance
b) It is affecting more on lower technology with poor performance
c) Dummy metal FILL in general have more minSpacing rule defined
d) Route blockage is not a layer number defined in GDS
e) Special layer defined for blocking the metal FILL, named EXCLUDE. This is increasing the spacing between metal layer. With the same amount Cc will reduced for more spacing

a) Comes for body bias connection
b) Noise current for the technology and body bias connection resistance creates the positive feedback loop which finally short circuit the power and ground.
c) BJT formed because of CMOS device structure, needed a trigger voltage.
d) This trigger voltage comes from the body bias resistance and noise current
e) BJT trigger voltage is fixed as device is fixed as per CMOS structure.
f) Maximum noise current is also fixed for technology.
g) Body bias resistance should be control to avoid latch issues.
h) This limit determines the maximum spacing b/w tap cells

DFM has two rules:

i. Recommended rules
ii. vios