a. DONE at post_cts (fixed vios upto -0.020) + post_route fix all vios (preferred)
b. DONE at post_route only

a. Having clock, from IO port (macro pin) to registers inside macro.

i. Required during CTS build (min and max insertion delay)

b. Transition and load information of all macro pins

i. Required for macro clock port during CTS build
ii. For other macro ports, these info required for correct timing computation

c. RISE, FALL, MIN, MAX : capacitance should be defined for all 4 case
d. Insertion delay : usually given in LIB/.DB
e. If not defined: timing violations will be seen when macro is become flat during STA.
f. Should block level insertion delay be higher than macro insertion delay?

a) Trace
b) Deletion
c) Buffer insertion as per Trans limit, tool maintain the more common path
d) Skew balance based on highest delay path

a. DRV (max_Transition, max_capacitance, fanout)
b. SKEW (local and Global)
c. Timing (setup and Hold)
d. Clock quality
e. Power

a. Clock gater always be at capture side, it cannot launch data to any flops.

i. Timing paths always be “TO clock gater”

b. What are the basic problems with clock gating vios

i. SKEW (launch clock path delay – capture clock path delay): where launch register is having higher clock path delay than clock gating cell.

c. Solutions:

i. Correct the SKEW problem:
1. Reduce the clock path delay of all launch register as per their timing violation. Use Float pin on all these startpoint CLK pin with positive value of the violation
2. Use below commands
3. get_timing_paths
ii. ENDPOINT BASED fixing
1. Endpoints are lesser in count
2. Margin needs to be there from the register getting driven by clock gater

a. Open nets
b. DRC (shorts and total DRCs)
c. DRVs
d. Timing
e. DFM / DFY

i. Design metal density
ii. Multicut vias
1. May cause hold vios after replacing single via to multi-cut via

a. Qor
b. Group-by-group
c. SKEW
d. Timing
e. SHORTS DRCs
f. DFM

a. 45-degree routing capability of the tool
b. Used for RDL routing or analog designs

a. Generally, tool will not leave any open.

i. If there are any special attributes defined on that net (skip_route, freeze)
ii. Reset these attribute and run commands (route_zrt_eco, ecoRoute)

b. Shorts:

i. Shorts with cell internal blockage

1. Move the cells if possible
2. Or run eco router again with settings to tool can identify these shorts.
3. BY TCL, create the full blockage at the short area. Run legalize placement
4. Power -signal: can be clean automatically by eco router
5. Power -power: cannot clean by tool
6. Power -ground: cannot clean by tool
7. Ground-ground: cannot clean by tool
8. CLOCK-Signal: eco router can clean this
9. CLOCK-CLOCK: eco route can clean this, ecoroute is not preferred here.

ii. Re-running the router commands also fix the shorts

1. Tool have left shorts because of maximum time approached
iii. Call ICV to fix shorts in ICC: signoff_autofix_drc

a. Starting utilization
b. Height & width
c. Total Die Area
d. ZIC timing (report_qor)
e. Macro orientation
f. Cell VT distribution (LVT, HVT)

i. All critical paths should be LVT
ii. get_cells -hier * -filter {ref_name=~*LVT*}

g. STD cells count & Area

i. get_cells -hier * -filter {mask_layout_type=~*std*}
ii. get_attribute
iii. foreach_in_collection

h. Macro count & Area
i. Buffer and inverter count & area
j. Clock buffers and inverter count & area
k. Hold buffers count & area