Q351. Factor in deciding the clock gating cell placement
a) Timing, start from register which is generating the enable signal and ending at clock gater (ICG or CGC)
b) CGC are placed during placement stage
c) Clock path delays are ZERO at placement stage
d) Data path delay will decide the clock gating placement
Q352. NDR, non-default routing rules.
a. Any change in default routing rule (minSpace, minWidth), is called NDR
b. WIDTH:
i. EM (electro migration)
ii. Low resistance
c. Spacing:
i. XTALK to data nets
ii. Only in specific condition where data net transition is faster than clock net, it may create XTALK on clock, Spacing is helping in reducing this XTALK.
Q353. Why is XTALK so important in design?
a) It effect hold and setup together as the polarity of XTALK is not fixed.
b) Setup path delay will increase with XTALK effect
c) Hold path delay will reduce with XTALK at the same time.
d) By fixing XTALK, it fixed the setup and hold path at the same time.
Q354. Why is spacing preferred over shielding of clock nets?
a. Shielding adds extra ground cap to clock nets which is increasing the load.
b. Shielding also consume more routing resource.
Q355. Is shielding or spacing hard constraints or soft constraints for clock nets?
a) This is soft constraints; tool will follow wherever space is available
b) Typically, in congested areas, these are not getting followed.
c) Clock nets always has more than 70% nets NDR honored
Q356. Why is shielding percentage reduced at post_route stage compares to CTS stage?
a. Difference between Routing estimation to actual routes
b. More areas become congested, so the NDR reduced in design.
c. STEPS:
i. Shielding is removed
ii. Actual routing of signal nets completed
iii. Shielding will be re-applied wherever it is possible.
Q357. Select the cells required for CTS
a. Main clock tree
b. Size_only
c. Delay insertion
Q358. Debug steps for hold fixing:
a) Review the list of cells given for hold fixing
b) Check that cells should be available (should not have dont_use attribute to 1)
c) Check the command to make these cells available for hold (set_prefer –min)
d) Check the hold corner is available
Q359. Fixing timing on clock gating vios:
a. Fixing on data path
b. Reduce clock insertion delay on startpoint (useful Skew / floatpin)
Q360. Command to report all vios to clock_gater
foreach_in_collection pin [all_fanin -to I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/EN -startpoints_only -flat] {report_timing -nosplit -nworst 1 -max_paths 1 -from [get_pins $pin] -to [get_pins I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/EN] >> ./clock_gate_vios.rpt }
