Automatically in TOOL:
i. Use useful Skew by adding float pin constraints on all the start point of the violating CGC. Apply the useful Skew as per the violation value.

Checks
a. All cells are legally placed, macro is already checked before placement
b. TILE: comes from Tech File
c. Design is divided into placement grid based on SITE/TILE
d. SITE_7T, SITE_8T, SITE_12T, HD, HP
e. Performance: HP, 12T cells at the cost of power and area
f. Area: HD, 7T at the cost of performance
g. Area with high performance design: 12T as performance is the main target
h. Target to battery operated device: 7T, HD
i. Target to battery operated device with high performance: 7T at the cost of higher area
j. Xbar architecture: maximum utilization for these arch are below 50%. These arch are net dominating
k. Cell dominating and net dominating
l. Starting utilization is depending on Architecture and given shape
m. Timing

i. WNS (worst negative slack)
ii. TNS (Total negative slack)
iii. FEP (failing endpoints)

n. Timing and congestion are going to degrade in further stage
i. Main reason for this is routing estimation at placement
o. Why is timing BAD at CTS?

i. Routing estimation
ii. Timing estimation (clock SKEW, in uncertainty of clocks)
iii. Placement level clock uncertainty: Jitter (fixed)+ SKEW (fixed) + distortion on clock path (fixed)
iv. CTS level clock uncertainty: Jitter (fixed)+ SKEW (depends on path) + distortion on clock path (depends on nos of levels, cells used)

p. Congestion

a) DB completed all placement checks
b) CTS target
c) CTS constraints
d) CTS cells
e) CTS NDR
f) CTS exceptions

a) Cells are legally placed
b) Cells used as per input given
c) Transition time on clock path
d) SKEW
e) Insertion delay
f) Timing
g) Congestion

a) SOC level insertion delay is hard requirement to meet (WIFI chip max insertion delay 5ns)
b) Balance clocks only for the blocks communicating
c) Clock transition is hard limit to meet for block

i. Sequential cell delay
ii. Tsetup and Thold requirement of the flop
iii. Lesser short ckt current
iv. For sharper trans time: bigger cells will be used which will consume more switching power
v. For sharper trans time: More number of levels

a. Communication to other blocks
b. It is must to decide and apply in design

a. MEM2REG paths for setup timing
b. REG2MEM paths for hold timing

a) NDR, which is consuming more routing tracks, it was not accounting in placement congestion estimation
b) Solution to this is “EARLY CLOCK” flow. This is used in lower technology which gives correct estimation of routing tracks requirement and STD cells area.
c) Another solution: reserve some percentage of tracks for each layer, impact the timing of design

a. Xtalk
b. Better skew
c. Lesser short ckt current

To avoid Xtalk on data nets.