Q331. What is need of critical range?
- It saves time of optimization
- As combinational logic is common to multiple paths, so tool need not to work on all paths
Q332. Difference between Hier and flat?
- Flat designs are preferred because of easy for optimization.
- Instance name is same in both the case (A/B/C/D).
- During flattening the design tool add hier as prefix to instance name.
- In flat design, difficult to divide the design for multi-cpu, multi-thread.
- In flat design, difficult to apply constraints for each module.
- Flat design is better for power, area, and timing.
- Flat design cannot be bigger in size.
- SoC level also division of blocks happened base on their hierarchies.
- Other checks like DFT, GLS also be having treble in identifying the constraints.
- Once design is flatten, it cannot be reverted back to original.
Q333. Why is DECAP called local supply source?
They get charge in normal cycle and supply the power in voltage drop condition.
Q334. Disadvantage of clock gating
a. Having extra check for timing
b. More design time for closure
Q335. Metal Layer allocation in design
a. Top:
i. Power to carry more current
b. Middle:
c. Bottom:
i. Uniform Distribution of power to STD cells
Q336. Pros and Cons of CTS scheme
a. Mesh:
i. More routing resource
ii. Robust for design variation
b. H tree:
i. Balance CTS
ii. More branches, more area, more power
Q337. Pros and cons of NDR
Pros:
- Xtalk (glitch, delay), net delay will be lesser for more width, EM with more width
- Report_timing -crosstalk_delay -net -input
- This will show the total net delay on input pin of each cell
- This delay component is total of net delay and Xtalk delay by using “-crosstalk_delay” option, it will print xtlak delay separately.
Cons:
- Congestion, extra route length
Q338. Why is mixing of VT types are not allowed in CTS?
Design variation are different for each VT type
Q339. Max Transition analysis
Check the driver,
i. reason: weak driver => upsize the driver
ii. reason: non-buffer element => insert buffer the driving pin
iii.reason: long wire length => insert buffer to break the net length as per buffer driving capability.
Q340. Why are metal layers taller in lower technology?
After reduction in width resistance gets increased with the same multiplier. To reduce the resistance on metal layer, it needs to increase the cross-sectional area. With is fixed for the give technology so metal height need to increase for this.
