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Physical Design Q&A

Q321. Placement results

1. Legalized cell placement
2. Congestion
3. density

Q322. Placement constraints

  • Placement blockage (partial, soft, hard)
  • Bounds (guide, region, fence)
  • Magnet placement
  • Relative placement
  • Keepout_margin/ padding

Q323. Placement Checks.

Legality of cell placement

Timing
  • Module placement
  • Path by path
Congestion
  • Congestion = (required tracks/available tracks)
  • Required tracks: reduce cell density, pin density, cris-cross in cell signal routing because of wrong cells placement for the path
  • Cell density: soft, partial, hard. Guide, region, fence, keep_out_margin
Density
  • PIN DENSITY
  • CELL DENSITY
    COND1: pin density is high and cell density is okay
  • Keep_out_margin
    COND2: pin density is okay and cell density is high
  • Soft, partial, hard
    COND3: pin and cell density both are high

Q324. Design starting utilization and congestion analysis

Starting utilization depends on type of architecture

  • Cell dominating, this will have more cell density
  • Net dominating, this will have lesser cell density


Cong = (Req/Avilable)
REQ:
  • Keeping placement constraints (BLK, Keepout)
  • De-tour nets crossing the critical area by adding buffer
Available:
  • Spacing given between macros OR std cells area
  • Type of power structure
    • Thick power stripe
    • Power stripes are not align to track
    • Clock NDR

    • Q325. Placement Output:

    • Timing
    • Congestion
    • Design density
    • Area
    • Power

    Q326. Placement Commands:

    • Visual check on the database
    • check_legality -verbose > chk_lega.rpt
    • report_qor > ./report_qor.rpt
    • report_timing –from [all_registers –clock_pin] –to [all_registers –data_pin] –net –trans – cap –nosplit –nworst 1 –max_path 1

    Q327. What is need of early clock (estimation of clock in placement) flow in PD in lower technology?

    • Early estimation of routing cong. and skew
    • It also reserves space for clock cells in CTS stage.

    Q328. What is banking and de-banking in synth and how this will help in saving power?

    • Banking: combining the REGs into one STD cell
    • DE-banking: separating the registers from bank
    • It is also called flop trays.

    Q329. What are the power strap vios in design?

    • How the power strap area treated for STD cells placement
    • ICC Tool has command called set_pnet_options
    • This is very serious for CTS cells because it leads to CTS cells routing change.
    • This command avoids shorts b/w cell internal blockage and power stripe

    Q330. Why is incremental optimization help in vios fixing?

    • Incr opt: is basically re-optimizing the optimized design
    • By running this, tool will again seeing the top paths as per new histogram.

    • What is synthesis?
    • Goals of synthesis
    • Synthesis Flow
    • Synthesis (input & output)
    • HDL file gen. & lib setup
    • Reading files
    • Design envi. Constraints
    • Compile
    • Generate Reports
    • Write files
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    • Netlist(.v or .vhd)
    • Constraints
    • Liberty Timing File(.lib or .db)
    • Library Exchange Format(LEF)
    • Technology Related files
    • TLU+ File
    • Milkyway Library
    • Power Specification File
    • Optimization Directives
    • Design Exchange Formats
    • Clock Tree Constraints/ Specification
    • IO Information File
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    • import design
    • sanity checks
    • partitioning (flat and hierarchy)
    • objectives of floorplan
    • Inputs of floorplan
    • Floorplan flowchart
    • Floorplan Techniques
    • Terminologies and definitions
    • Steps in FloorPlan
    • Utilization
    • IO Placement
    • Macro Placement
    • Macro Placement Tips
    • Blockages (soft,hard,partial)
    • Halo/keepout margin
    • Issues arises due to bad floor-plan)
    • FloorPlan Qualifications
    • FloorPlan Output
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    • levels of power distribution
    • Power Management
    • Powerplanning involves
    • Inputs of powerplan
    • Properties of ideal powerplan
    • Power Information
    • PowerPlan calculations
    • Sub-Block configuration
    • fullchip configuration
    • UPF Content
    • Isolation Cell
    • Level Shifters
    • Retention Registers
    • Power Switches
    • Types of Power dissipation
    • IR Drop
    • Electromigration
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    • Pre-Placement
    • Pre-Placement Optimization
    • Placement
    • Placement Objectives
    • Goals of Placement
    • Inputs of Placement
    • Checks Before placement
    • Placement Methods(Timing & Congestion)
    • Placement Steps
    • Placement Optimization
    • Placement Qualifications
    • Placement Outputs
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    • Pre-CTS Optimization
    • CTS
    • Diff b/w HFNS & CTS
    • Diff b/w Clock & normal buffer
    • CTS inputs
    • CTS Goals
    • Clock latency
    • Clock problems
    • Main concerns for Clock design
    • Clock Skew
    • Clock Jitter
    • CTS Pre requisites
    • CTS Objects
    • CTS Flow
    • Clock Tree Reference
    • Clock Tree Exceptions
    • CTS Algorithm
    • Analyze the Clock tree
    • Post CTS Optimization
    • CTS Outputs
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    • Importance of Routing as Technology Shrinks
    • Routing Objectives
    • Routing
    • Routing Inputs
    • Routing Goals
    • Routing constraints
    • Routing Flow
    • Trial/Global Routing
    • Track Assignment
    • Detail/Nano Routing
    • Grid based Routing
    • Routing Preferences
    • Post Routing Optimization
    • Filler Cell Insertion
    • Metal Fill
    • Spare Cells Tie-up/ Tie-down
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    • Diff b/w DTA & STA
    • Static Timing Analysis
    • main steps in STA
    • STA(input & output)
    • Timing Report
    • Clocked storage elements
    • Delays
    • Pins related to clock
    • Timing Arc
    • Timing Unate
    • Clock definitions in STA
    • Timing Paths
    • Timing Path Groups
    • Clock Latency
    • Insertion Delay
    • Clock Uncertainty
    • Clock Skew
    • Clock Jitter
    • Glitch
    • Pulse width
    • Duty Cycle
    • Transition/Slew
    • Asynchronous Path
    • Critical Path
    • Shortest Path
    • Clock Gating Path
    • Launch path
    • Arrival Path
    • Required Time
    • Common Path Pessimism(CPP/CRPR)
    • Slack
    • Setup and Hold time
    • Setup & hold time violations
    • Recovery Time
    • Removal Time
    • Recovery & Removal time violations
    • Single Cycle path
    • Multi Cycle Path
    • Half Cycle Path
    • False Path
    • Clock Domain Crossing(CDC)
    • Clock Domain Synchronization Scheme
    • Bottleneck Analysis
    • Multi-VT Cells(HVT LVT SVT)
    • Time Borrowing/Stealing
    • Types of STA (PBA GBA)
    • Diff b/w PBA & GBA
    • Block based STA & Path based STA
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    • Congestion Analysis
    • Routing Congestion Analysis
    • Placement Cong. Analysis
    • Routing Congestion causes
    • Congestion Fixes
    • Global & local cong.
    • Congestion Profiles
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    • Power Analysis
    • Leakeage Power
    • Switching Power
    • Short Circuit
    • Leakage/static Power
    • Static power Dissipation
    • Types of Static Leakage
    • Static Power Reduction Techniques
    • Dynamic/Switching Power
    • Dynamic Power calculation depends on
    • Types of Dynamic Power
    • Dynamic Power Reduction Techniques
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    • IR Drop Analysis
    • Types of IR Drop & their methodologies
    • IR Drop Reasons
    • IR Drop Robustness Checks
    • IR Drop Impacts
    • IR Drop Remedies
    • Ldi/dt Effects
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    • Design Parasitics
    • Latch-Up
    • Electrostatic Discharge(ESD)
    • Electromigration
    • Antenna Effect
    • Crosstalk
    • Soft Errors
    • Sef Heating
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    • Cells in PD
    • Standard Cells
    • ICG Cells
    • Well Taps
    • End Caps
    • Filler Cells
    • Decap Cells
    • ESD Clamp
    • Spare Cells
    • Tie Cells
    • Delay Cells
    • Metrology Cells
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    • IO Pads
    • Types of IO Pads
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    • Delay Calculation
    • Delay Models
    • Interconnect Delay Models
    • Cell Delay Models
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    • Engineering Change Order
    • Post Synthesis ECO
    • Post Route ECO
    • Post Silicon ECO
    • Metal Layer ECO Example
    Go To page
    • std cell library types
    • Classification wrt density and Vth
    Go To page

    • The Discontinuity
    • Discontinuity: Classification
    • DFM/DFY
    • Yield Classification
    • Why DFM/DFY?
    • DFM/DFY Solution
    • Wire Spreading
    • metal Fill
    • CAA
    • CMP Aware-Design
    • Redundant Via
    • RET
    • Litho Process Check(LPC)
    • Layout Dependent Effects
    • Resolution Enhancement Techniques
    • Types of RET
    • Optical Proximity Correction(OPC)
    • Scattering Bars
    • Multiple Patterning
    • Phase-shift Masking
    • Off-Axis Illumination
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    • Corners
    • Need for corner analysis
    • PVT Variations
    • Corner Analysis
    • PVT/RC Corners
    • Temperature Inversion
    • Cross Corner Analysis
    • Modes of Analysis
    • MC/MM Analysis
    • OCV
    • Derating
    • OCV Timing Checks
    • OCV Enhancements
    • AOCV
    • SSTA
    • CRPR/CPPR
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