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Physical Design Q&A

Q311. Can it be same launch – capture path be critical?

a. For same PVT, NO
b. For different PVT, YES
    i. Delay scaling is not uniform for different voltage.
    ii. Delay at 0.5 v can be 10X than delay at 2.0v
    iii. Choose the cells which are having lesser scaling effect for all these paths

Q312. What is the need of MV designs?

a. By reducing voltage, CMOS consume less power ({1/2}*a*C*V^2)
b. Voltage:
    i. More levels based on requirement
    ii. Active power
c. Activity (toggle)
    i. Clock gating
d. ON-OFF domain
    i. Power saving (leakage)

Q313. Why is ISO required for ON-OFF design?

a. Signal ON->OFF
    i. NO ISSUES
b. Signal OFF->ON
    i. Problem of determining the input state, it propagate X in system
    ii. Short the power ground for the CMOS whose input will be in middle
c. Short circuit current
    i. ISO cells (OR, AND) will change the signal to fixed value (0 : AND, 1: OR)

Q314. What are the cells used in low power cells techniques?

a. ISO
b. LS
c. Power switch

Q315. What is the difference b/w VA and power domain?

When design area is assigned to power domain, it is called VA.

Q316. How do you know that you design is SW design by checking all design inputs?

There will be a “create_isolation_rule” in UPF

Q317. How to find the design needed power switch?

UPF will be having “create_power_switch” command with the control signal defined

Q318. What are the power saving techniques?

a. Voltage
    i. Power domain ON-OFF
    ii. Adaptive power supply, apply power supply based on function requirement
b. Switching
    i. Bit assignment in architecture
    ii. PD tool, place cells based on switching
    iii. Switching power: Clock gating

Q319. Placement Targets

1. Meeting timing (WNS {worst negative slack}, TNS {total negative slack}, FEP{failing end points) mainly for REG2REG)
2. Congestion in limit (0.5% H, V; lower tech hotspot: Total < 10000, max < 200)
3. Cell density
4. Pin density

Q320. Placement Inputs

1. FP completed design
2. SDC, MMMC
3. Design targets (max_trans, max_area)

  • What is synthesis?
  • Goals of synthesis
  • Synthesis Flow
  • Synthesis (input & output)
  • HDL file gen. & lib setup
  • Reading files
  • Design envi. Constraints
  • Compile
  • Generate Reports
  • Write files
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  • Netlist(.v or .vhd)
  • Constraints
  • Liberty Timing File(.lib or .db)
  • Library Exchange Format(LEF)
  • Technology Related files
  • TLU+ File
  • Milkyway Library
  • Power Specification File
  • Optimization Directives
  • Design Exchange Formats
  • Clock Tree Constraints/ Specification
  • IO Information File
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  • import design
  • sanity checks
  • partitioning (flat and hierarchy)
  • objectives of floorplan
  • Inputs of floorplan
  • Floorplan flowchart
  • Floorplan Techniques
  • Terminologies and definitions
  • Steps in FloorPlan
  • Utilization
  • IO Placement
  • Macro Placement
  • Macro Placement Tips
  • Blockages (soft,hard,partial)
  • Halo/keepout margin
  • Issues arises due to bad floor-plan)
  • FloorPlan Qualifications
  • FloorPlan Output
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  • levels of power distribution
  • Power Management
  • Powerplanning involves
  • Inputs of powerplan
  • Properties of ideal powerplan
  • Power Information
  • PowerPlan calculations
  • Sub-Block configuration
  • fullchip configuration
  • UPF Content
  • Isolation Cell
  • Level Shifters
  • Retention Registers
  • Power Switches
  • Types of Power dissipation
  • IR Drop
  • Electromigration
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  • Pre-Placement
  • Pre-Placement Optimization
  • Placement
  • Placement Objectives
  • Goals of Placement
  • Inputs of Placement
  • Checks Before placement
  • Placement Methods(Timing & Congestion)
  • Placement Steps
  • Placement Optimization
  • Placement Qualifications
  • Placement Outputs
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  • Pre-CTS Optimization
  • CTS
  • Diff b/w HFNS & CTS
  • Diff b/w Clock & normal buffer
  • CTS inputs
  • CTS Goals
  • Clock latency
  • Clock problems
  • Main concerns for Clock design
  • Clock Skew
  • Clock Jitter
  • CTS Pre requisites
  • CTS Objects
  • CTS Flow
  • Clock Tree Reference
  • Clock Tree Exceptions
  • CTS Algorithm
  • Analyze the Clock tree
  • Post CTS Optimization
  • CTS Outputs
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  • Importance of Routing as Technology Shrinks
  • Routing Objectives
  • Routing
  • Routing Inputs
  • Routing Goals
  • Routing constraints
  • Routing Flow
  • Trial/Global Routing
  • Track Assignment
  • Detail/Nano Routing
  • Grid based Routing
  • Routing Preferences
  • Post Routing Optimization
  • Filler Cell Insertion
  • Metal Fill
  • Spare Cells Tie-up/ Tie-down
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  • Diff b/w DTA & STA
  • Static Timing Analysis
  • main steps in STA
  • STA(input & output)
  • Timing Report
  • Clocked storage elements
  • Delays
  • Pins related to clock
  • Timing Arc
  • Timing Unate
  • Clock definitions in STA
  • Timing Paths
  • Timing Path Groups
  • Clock Latency
  • Insertion Delay
  • Clock Uncertainty
  • Clock Skew
  • Clock Jitter
  • Glitch
  • Pulse width
  • Duty Cycle
  • Transition/Slew
  • Asynchronous Path
  • Critical Path
  • Shortest Path
  • Clock Gating Path
  • Launch path
  • Arrival Path
  • Required Time
  • Common Path Pessimism(CPP/CRPR)
  • Slack
  • Setup and Hold time
  • Setup & hold time violations
  • Recovery Time
  • Removal Time
  • Recovery & Removal time violations
  • Single Cycle path
  • Multi Cycle Path
  • Half Cycle Path
  • False Path
  • Clock Domain Crossing(CDC)
  • Clock Domain Synchronization Scheme
  • Bottleneck Analysis
  • Multi-VT Cells(HVT LVT SVT)
  • Time Borrowing/Stealing
  • Types of STA (PBA GBA)
  • Diff b/w PBA & GBA
  • Block based STA & Path based STA
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  • Congestion Analysis
  • Routing Congestion Analysis
  • Placement Cong. Analysis
  • Routing Congestion causes
  • Congestion Fixes
  • Global & local cong.
  • Congestion Profiles
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  • Power Analysis
  • Leakeage Power
  • Switching Power
  • Short Circuit
  • Leakage/static Power
  • Static power Dissipation
  • Types of Static Leakage
  • Static Power Reduction Techniques
  • Dynamic/Switching Power
  • Dynamic Power calculation depends on
  • Types of Dynamic Power
  • Dynamic Power Reduction Techniques
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  • IR Drop Analysis
  • Types of IR Drop & their methodologies
  • IR Drop Reasons
  • IR Drop Robustness Checks
  • IR Drop Impacts
  • IR Drop Remedies
  • Ldi/dt Effects
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  • Design Parasitics
  • Latch-Up
  • Electrostatic Discharge(ESD)
  • Electromigration
  • Antenna Effect
  • Crosstalk
  • Soft Errors
  • Sef Heating
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  • Cells in PD
  • Standard Cells
  • ICG Cells
  • Well Taps
  • End Caps
  • Filler Cells
  • Decap Cells
  • ESD Clamp
  • Spare Cells
  • Tie Cells
  • Delay Cells
  • Metrology Cells
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  • IO Pads
  • Types of IO Pads
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  • Delay Calculation
  • Delay Models
  • Interconnect Delay Models
  • Cell Delay Models
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  • Engineering Change Order
  • Post Synthesis ECO
  • Post Route ECO
  • Post Silicon ECO
  • Metal Layer ECO Example
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  • std cell library types
  • Classification wrt density and Vth
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  • The Discontinuity
  • Discontinuity: Classification
  • DFM/DFY
  • Yield Classification
  • Why DFM/DFY?
  • DFM/DFY Solution
  • Wire Spreading
  • metal Fill
  • CAA
  • CMP Aware-Design
  • Redundant Via
  • RET
  • Litho Process Check(LPC)
  • Layout Dependent Effects
  • Resolution Enhancement Techniques
  • Types of RET
  • Optical Proximity Correction(OPC)
  • Scattering Bars
  • Multiple Patterning
  • Phase-shift Masking
  • Off-Axis Illumination
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  • Corners
  • Need for corner analysis
  • PVT Variations
  • Corner Analysis
  • PVT/RC Corners
  • Temperature Inversion
  • Cross Corner Analysis
  • Modes of Analysis
  • MC/MM Analysis
  • OCV
  • Derating
  • OCV Timing Checks
  • OCV Enhancements
  • AOCV
  • SSTA
  • CRPR/CPPR
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