Q301. Steps to solve multi-cycle problems?
a. Draw launch and capture waveform with ideal clock.
b. Mark the active edges for launch and capture.
c. Fix the current active launch edge.
d. Mark the number of cycles in capture active edges.
e. Select the setup check edges as per the given constraint.
f. Setup check needs to shift number of cycle forward for setup.
g. Hold check needs to be shift (numbers of cycle – 1) cycle backward.
Q302. Steps in fixing the setups timing:
a. Review clock skew
b. Optimize Data path first
c. Look for clock skewing (floating pin / useful Skew)
d. Useful Skew at launch flop:
i. Timing margin to launch flop
e. Useful Skew at capture flop
i. Timing margin from capture flop
Q303. SPEF EXTRACTION
a. INPUTS: SPEF,. V, .SDC, .DBs + MACRO.V (if macro needs to be flat)
b. INPUTS FOR GENERATION: NXTGRD, Mapping, MW_LIB OR DEF + MACRO.def (if macro needs to be flat): ALSO CALLED FLAT EXTRATION
i. Required: metal layer, via information
ii. Cap, resistance model
iii. Mapping file iv. LEF or FRAM view
c. OUTPUT OF STARRC:
i. SPEF
ii. Open and shorts information
d. SPEF STICH:
i. MACRO SPEF will be used for macro internal RC values.
ii. Multiple spef files will be there
iii. Read all lower level SPEF before main SPEF file
iv. SAVING on SPEF GENERATION TIME and CPU Usage
v. Lesser accuracy compare to FLAT extraction
Q304. Case_analysis
set_case_analysis 0 [get_ports SCAN_EN]
i. DEFINED IN SDC file
ii. Propagating the logic value till MUX to make decision on MODEs of operation
iii. Assignment: check the case_analysis given in SDC
1. cd /home/root………./design_data/
2. grep “case_analy” *.sdc (when present directory is data directory)
3. grep “case_analy” /home/root………./design_data/*.sdc
Q305. What are the valid start points of any design?
a. INPUT PORT
b. CLK pin of FLOP
Q306. What are the valid endpoints?
a. OUTPUT PORT
b. FLOP data pin (d pin)
Q307. Why is derate applied only on capture clock path?
a. Set_timing_derate -early: only capture clock is min for setup.
b. All variations are applied to capture side.
Q308. Why is DFF used over JK flops?
RACE condition
Q309. Useful Skew
a. Required whenever there is no scope of optimization on data path
b. Useful Skew on Launch path:
i. Many start points needs to be early
ii. Some cases difficult to make clock early as it may violate transition
iii. Condition: +ve setup slack to launch register
c. Useful Skew on capture path:
i. Preferred as STA analysis is done based on endpoint and lesser endpoint count
ii. Increase the capture clock path delay
iii. Relatively easier to increase the clock delay
iv. Condition: +ve setup slack from capture flop
Q310. Hold fixing after tapeout?
a. Missing timing arc
b. In all other condition, there is no scope of fixing the hold.
