Q291. How to decide metal layer for power planning?
a. Frequency
b. Architecture (CPU, DSP): switching
c. IR drop
Q292. Top down vs bottom -up:
a. Priority is design closure
b. Data comes from top to bottom
c. Feedback goes bottom to top
d. FROM TOP
i. DIE initial shape
ii. All initial ports placement
e. To TOP;
i. Final design shape
ii. Final ports placement
Q293. How to avoid Xtalk
Comes with more parallel length
i. Reduce parallel length by change metal layer.
ii. Create more spacing to reduce coupling cap.
iii. Insert buffer to strength the net.
iv. report_timing –corsstalk_delay.
v. report_noise_calculation.
Q294. How to fix hold after routing?
a. Adding buffer
b. Enable the view , route_opt –hold,
Q295. DRV vs setup, hold; which will have more priority
a. DRV: must fix,
i. Seq data pins having tighter limit for transition
b. Setup: depends on frequency target
c. Hold: must fix, design will fail for these vios
Q296. What is what-if analysis in STA?
a. Manually targeting cells in design for timing fixing and measuring the impact of them in design, is called what-if analysis.
b. This can be for any design target
Q297. What is the difference between “nworst 1” and “max_path 1” in report_timing command?
a. “max_path 1” reports only the top violating path which is my WNS path for that respective group.
b. “nworst 1” is reporting worst path per end point for each defined group
Q298. Timing categorise:
a. REG2REG
i. Preferred, mainly focus on this in block level
b. IN2REG
c. REG2OUT
d. IN2OUT
e. Timing groups defined by user f. Tool by-default create path groups based on clock defined in design
Q299. Steps to solve any setup and hold problems?
a. Draw the waveforms for launch and capture
b. If skew is not given, draw clocks as ideal clocks
c. Mark the active edges for launch and capture
d. Mark the setup checks (1 cycle)
e. Mark the hold check (hold checks will have done between current launch active edge and previous capture active edge).
Q300. Multi-Cycle Path HOLD and Setup violation fixing techniques.
a. It determined by data path delay, if delay is much higher than clock period.
b. Data path is as per coded architecture.
c. Only Arch will clarify on these constraints for any doubts.
d. This is a timing constraint which is instructing the STA tool to check setup and hold as per given cycles.
e. Default setup checks will be done one cycle.
f. Default hold check will be done between current active edge of launch and previous active edge of capture.
