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Physical Design Q&A

Q281. Things needs to be reset in design

a. POWER related error
    i. reset_upf
    ii. load_upf ORCA_TOP.upf

b. operating condition
    i. get_app_var *continue*
    ii. set_app_var continue_on_operating_mismatch true

c. cells are overlap after placement
    i. remove_sdc
    ii. remove_scenario -all
    iii. source mmmc.scenario.tcl (found in prj1.FP.manual.tcl)
    iv. remove_pnet_options

Q282. Limitations on power via.

a. Based on metal width via array will be selected
b. As per technology, via staking will be selected.

Q283. Why is routing blockage defined at DIE edge?

a. This is mainly for tool to avoid any routes goes outside the DIE area.
b. This also help in keeping routes well within design to avoid DRCs at DIE boundary.

Q284. Why is TAP cells required?

a. LATCH issue
b. At 65nm TAP cells start using
c. Above 65nm, each STD cells has its own body connection.
d. It was difficult to shrink the STD cells with body bias contact.
e. Body bias connection is required at interval of um.
f. By keeping body bias contact, it will be easy to shrink the CMOS.
g. This body bias connection was provided by TAP cell.
h. By placing them in checker board fashion, total cells requirement reduced to ~half.

Q285. What is the type of physical only cells in design?

a. ENDCAP: nwell ending
b. TAP cells: body bias contact
c. DECAP: local power source
d. SPARE cells / programmable cells
e. FILLERs: nwell continuity
f. ESD cells as MACRO for flipchip design
g. Navigation marker cells
h. Foundry cells for testing the metal layer and CMOS layers

Q286. Why is CORE to DIE spacing required in all sides?

a. PORTs
b. Avoid shorts b/w blocks
c. Noise b/w blocks

Q287. What is the factor limiting the macro orientation in design?

POLY manufacturing accuracy

Q288. Is Macro needs to aligned to STD rows?

a. NO
b. STD ROW are reference grid for the placement engine to place STD cells
c. This is not required for MACROS

Q289. Can macro be placed at DIE boundary?

YES, if macro owner the CORE -DIE boundary spacing rule.

Q290. Can there be macro in IO placement area in FULL chip?

Yes, with proper power planning for IO pads.

  • What is synthesis?
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  • Netlist(.v or .vhd)
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  • import design
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  • levels of power distribution
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  • Pre-Placement
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  • Importance of Routing as Technology Shrinks
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  • Diff b/w DTA & STA
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  • Congestion Analysis
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  • Power Analysis
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  • IR Drop Analysis
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  • Design Parasitics
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  • Cells in PD
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  • IO Pads
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  • Delay Calculation
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  • Engineering Change Order
  • Post Synthesis ECO
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  • std cell library types
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  • The Discontinuity
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  • Corners
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