Physical Design Q&A

Q271. Why is LOOKUP table used for .libs?

a. Easy access
b. Less memory consumption
c. Accuracy will be lesser for inputs which is out of range

Q272. What is the information capture in LIB?

a. Input capacitance
b. Leakage power under all condition
c. Functionality of the cell
d. Output transition in Look up table format
e. Cell delay table
f. Insertion delay table for macros [ always verify this in CTS stage]

Q273. What is the information capture in LEF?

a. SIZE
b. TILE
c. Symmetry
d. OBS
e. PIN BOX with layer
f. Origin

Q274. Why is thick metal layer need more spacing?

These thick layer has more chance of variation in manufacturing.

Q275. What is the use of TLU-PLUS files?

It contains RC models, with the help of this ICC compute the RC delay.

Q276. What is mapping file and where all it is required?

a. It is aliasing file to make other tool understand about metal layer used in PD tool.
b. STAR-RC.
c. To dump GDS file from tool.

Q277. How to create basic SDC for any new design?

a. Import the Verilog in ICC
b. Get all the clock ports
c. Define clock on these ports
d. Run check_timing and clean the errors reported
e. Define IO cons
    i. set_input_deriving_cell
    ii. set_input_transition
    iii. set_load
    iv. set_input_delay
    v. set_output_delay

Q278. How to validate SDC?

a. Multi-cycle paths
    i. Setup 3 cycle
    ii. Hold 2 cycle
b. 2 flop Synchronizer
    i. Always have Multi-cycle for 2 cycle to capture data
    ii. Hold check will be having multicycle of 1
c. Review all false paths in SDC

Q279. What happen if one AND gate is not having timing arc in lib and used in design?

a. Design will fail for this these paths through AND cell, as paths will not be seen and optimize.
b. Log file has warnings for this issue for missing timing arc.

Q280. Create_generated_clock -invert/-combination

a. Default create_genearted_clock goes through sequential cells
b. By specifying -combinational options, generated clock will be traced through combinational cells
  • What is synthesis?
  • Goals of synthesis
  • Synthesis Flow
  • Synthesis (input & output)
  • HDL file gen. & lib setup
  • Reading files
  • Design envi. Constraints
  • Compile
  • Generate Reports
  • Write files
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  • Netlist(.v or .vhd)
  • Constraints
  • Liberty Timing File(.lib or .db)
  • Library Exchange Format(LEF)
  • Technology Related files
  • TLU+ File
  • Milkyway Library
  • Power Specification File
  • Optimization Directives
  • Design Exchange Formats
  • Clock Tree Constraints/ Specification
  • IO Information File
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  • import design
  • sanity checks
  • partitioning (flat and hierarchy)
  • objectives of floorplan
  • Inputs of floorplan
  • Floorplan flowchart
  • Floorplan Techniques
  • Terminologies and definitions
  • Steps in FloorPlan
  • Utilization
  • IO Placement
  • Macro Placement
  • Macro Placement Tips
  • Blockages (soft,hard,partial)
  • Halo/keepout margin
  • Issues arises due to bad floor-plan)
  • FloorPlan Qualifications
  • FloorPlan Output
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  • levels of power distribution
  • Power Management
  • Powerplanning involves
  • Inputs of powerplan
  • Properties of ideal powerplan
  • Power Information
  • PowerPlan calculations
  • Sub-Block configuration
  • fullchip configuration
  • UPF Content
  • Isolation Cell
  • Level Shifters
  • Retention Registers
  • Power Switches
  • Types of Power dissipation
  • IR Drop
  • Electromigration
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  • Pre-Placement
  • Pre-Placement Optimization
  • Placement
  • Placement Objectives
  • Goals of Placement
  • Inputs of Placement
  • Checks Before placement
  • Placement Methods(Timing & Congestion)
  • Placement Steps
  • Placement Optimization
  • Placement Qualifications
  • Placement Outputs
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  • Pre-CTS Optimization
  • CTS
  • Diff b/w HFNS & CTS
  • Diff b/w Clock & normal buffer
  • CTS inputs
  • CTS Goals
  • Clock latency
  • Clock problems
  • Main concerns for Clock design
  • Clock Skew
  • Clock Jitter
  • CTS Pre requisites
  • CTS Objects
  • CTS Flow
  • Clock Tree Reference
  • Clock Tree Exceptions
  • CTS Algorithm
  • Analyze the Clock tree
  • Post CTS Optimization
  • CTS Outputs
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  • Importance of Routing as Technology Shrinks
  • Routing Objectives
  • Routing
  • Routing Inputs
  • Routing Goals
  • Routing constraints
  • Routing Flow
  • Trial/Global Routing
  • Track Assignment
  • Detail/Nano Routing
  • Grid based Routing
  • Routing Preferences
  • Post Routing Optimization
  • Filler Cell Insertion
  • Metal Fill
  • Spare Cells Tie-up/ Tie-down
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  • Diff b/w DTA & STA
  • Static Timing Analysis
  • main steps in STA
  • STA(input & output)
  • Timing Report
  • Clocked storage elements
  • Delays
  • Pins related to clock
  • Timing Arc
  • Timing Unate
  • Clock definitions in STA
  • Timing Paths
  • Timing Path Groups
  • Clock Latency
  • Insertion Delay
  • Clock Uncertainty
  • Clock Skew
  • Clock Jitter
  • Glitch
  • Pulse width
  • Duty Cycle
  • Transition/Slew
  • Asynchronous Path
  • Critical Path
  • Shortest Path
  • Clock Gating Path
  • Launch path
  • Arrival Path
  • Required Time
  • Common Path Pessimism(CPP/CRPR)
  • Slack
  • Setup and Hold time
  • Setup & hold time violations
  • Recovery Time
  • Removal Time
  • Recovery & Removal time violations
  • Single Cycle path
  • Multi Cycle Path
  • Half Cycle Path
  • False Path
  • Clock Domain Crossing(CDC)
  • Clock Domain Synchronization Scheme
  • Bottleneck Analysis
  • Multi-VT Cells(HVT LVT SVT)
  • Time Borrowing/Stealing
  • Types of STA (PBA GBA)
  • Diff b/w PBA & GBA
  • Block based STA & Path based STA
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  • Congestion Analysis
  • Routing Congestion Analysis
  • Placement Cong. Analysis
  • Routing Congestion causes
  • Congestion Fixes
  • Global & local cong.
  • Congestion Profiles
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  • Power Analysis
  • Leakeage Power
  • Switching Power
  • Short Circuit
  • Leakage/static Power
  • Static power Dissipation
  • Types of Static Leakage
  • Static Power Reduction Techniques
  • Dynamic/Switching Power
  • Dynamic Power calculation depends on
  • Types of Dynamic Power
  • Dynamic Power Reduction Techniques
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  • IR Drop Analysis
  • Types of IR Drop & their methodologies
  • IR Drop Reasons
  • IR Drop Robustness Checks
  • IR Drop Impacts
  • IR Drop Remedies
  • Ldi/dt Effects
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  • Design Parasitics
  • Latch-Up
  • Electrostatic Discharge(ESD)
  • Electromigration
  • Antenna Effect
  • Crosstalk
  • Soft Errors
  • Sef Heating
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  • Cells in PD
  • Standard Cells
  • ICG Cells
  • Well Taps
  • End Caps
  • Filler Cells
  • Decap Cells
  • ESD Clamp
  • Spare Cells
  • Tie Cells
  • Delay Cells
  • Metrology Cells
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  • IO Pads
  • Types of IO Pads
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  • Delay Calculation
  • Delay Models
  • Interconnect Delay Models
  • Cell Delay Models
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  • Engineering Change Order
  • Post Synthesis ECO
  • Post Route ECO
  • Post Silicon ECO
  • Metal Layer ECO Example
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  • std cell library types
  • Classification wrt density and Vth
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  • The Discontinuity
  • Discontinuity: Classification
  • DFM/DFY
  • Yield Classification
  • Why DFM/DFY?
  • DFM/DFY Solution
  • Wire Spreading
  • metal Fill
  • CAA
  • CMP Aware-Design
  • Redundant Via
  • RET
  • Litho Process Check(LPC)
  • Layout Dependent Effects
  • Resolution Enhancement Techniques
  • Types of RET
  • Optical Proximity Correction(OPC)
  • Scattering Bars
  • Multiple Patterning
  • Phase-shift Masking
  • Off-Axis Illumination
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  • Corners
  • Need for corner analysis
  • PVT Variations
  • Corner Analysis
  • PVT/RC Corners
  • Temperature Inversion
  • Cross Corner Analysis
  • Modes of Analysis
  • MC/MM Analysis
  • OCV
  • Derating
  • OCV Timing Checks
  • OCV Enhancements
  • AOCV
  • SSTA
  • CRPR/CPPR
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