Q261. If you are failing transition on a net routed over a macro. How do you fix transition with minimal rerouting?
- Layer promotion
- Increasing driver strength
- Downsizing sinks
- Load Splitting
- Delete net/nets around the violating net with positive setup/hold margins and slew margin and Re-global route it to see if there are any alternative ways to route the nets around the macro and then buffer it.
Q262. What is the short circuit current? How transition affects short circuit current
- A rising signal is applied at input of CMOS inverter. As the signal transitions from low to high, the N type transistor turns on when Vgs > Vtn and the P type transistor turns off. However, for a short time during signal transition, both the P and N type transistors can be on simultaneously when Vtn < Vgs < VDD-Vtp. During this time, current Isc flows from Vdd to GND. This current is called short circuit current causes the dissipation of short-circuit power (Psc). Or When input voltage is between Vtn and VDD-|Vtp|, both PMOS and NMOS will be open for a short period of time, which causes a current flow from VDD to VSS. This is called short circuit current and power dissipated due to this is called short circuit power.
- For circuits with fast transition times, short-circuit power can be small. However, for circuits with slow transition times, short-circuit power can account for 30 percent of the total power dissipated by the gate. Short-circuit power is affected by the dimensions of the transistors and the load capacitance at the gate’s output.
Q263. what is AWP (advance wave propagation)
Signal waveforms gets distorted at the input of the receiver due to miller affect and long tail affect. Cell delays will be optimistic If we don’t consider these affects. We need to enable AWP with time. delay_calc_waveform_analysis_mode for better and accurate cell delay values. We need to provide ccs timing and ccs noise models for this purpose.
Q264. In case, if you have access to only timing report at post route. What are the factors you will look into to improve setup timing?
First of all, check whether timing path is real of false path by checking the clocks. If both launch & capture belongs to same clock group, then see whether they their clock pins balanced properly with less skew or not. If common clock path is less, then ocv derates will make the timing close difficult as skew will be more due to that. Similarly, if launch & capture belongs to different clock domains, check with the designer if this path is valid or not. If it is valid and then these clocks were not balanced and not in the same skew group, then try to build CTS with better skew improvement. After this, will check data path. Check data path has any low drive strength cells with bad transition, it means, tool didn't do better job or tool couldn’t able to upsize them due to high cell density. If data path has large buffer/inverter chain, then detour happened due to congestion in the design and fixed DRV fixes on these nets by adding buffer chan. So address congestion to improve timing
a) Look at delta derate delay, if you see more then reduce net length during optimization and If you see more clock use better NDR rule
b) More cell delay can be improved by avoiding low drive strength cells.
c) Look at the skew, if more can be improved during CTS
d) setup time and clk->q access time of flop or memory need to be checked.
Q265. What are the design issues with higher Input transition?
a. Higher output transition
b. Higher cell delay
Q266. What is the difference between drive strength and fanout?
a. Driving capability:
i. how much maximum capacitance a device can drive
ii. It is captured in .lib as max_capacitance
b. Fanout:
i. These are the number of gates drive
ii. Device models will decide the fanout
iii. Technology variation also decide
Q267. What is the need of models in CMOS design?
a. Faster computation
b. Accurate computation
Q268. What are the inputs for .lib?
a. Input transition
b. Output load
Q269. What are the outputs of .lib?
a. Output Transition
b. Cell delay
Q270. Why is input capacitance similar for higher drive?
a. All STD cells are designed in two stage [1stage => 2stage]
b. 1 st stage which is mainly for functionality of the cell
c. 2 nd stage is for driving capability of the cell
d. For higher drive cells, only 2nd stage gets more strengthen
e. As 1st stage is not getting change much so input capacitance are similar
