Physical Design Question & Answers | Q&A |Physical Design| VLSI Back-End Adventure

Physical Design Q&A

Q251. What are the recommended settings for designs with complex or fragmented floorplans?

Enable global-route-based high-fanout synthesis for the place_opt command, which can improve routability and reduce congestion, by using the following setting:
set_app_options -list {place_opt.initial_drc.global_route_based 1}
Enable two-pass flow for the place_opt command, which generates a better initial placement, by using the following setting:
set_app_options -list {place_opt.initial_place.two_pass true}
Enable global routing for initial clock tree synthesis, which improves congestion estimation and perform congestion aware clock tree construction, by using the following setting: set_app_options -list {cts.compile.enable_global_route true}

Note: Steps 1 and 2 should only be used if you are not using the Synopsys physical guidance (SPG) flow.

Q252. What will you look for netlist while floor planning?

Look for macros
Group macros acc to hierarchy
Space the macros according to the no of pins
make sure you have VDD/VSS set b/w macros
Put soft blockages in channels to avoid flops being placed
Add density screen if needed.

Q253. TCL proc for palindrome

proc check_palindrome {in_str} {
set str_len [string length $in_str]
set str_mid [expr $str_len/2]
for {set i 0} {$i < $str_mid} {incr i} {
if {[string index $in_str $i] != [string index $in_str end-$i]} {
puts "$in_str is not a palindrome"
return
}
}
puts "$in_str is a palindrome"
}

Q254. How to open a file and print line starting with error?

set f [open x.txt r]
while { [gets $f line] > 0 }
{
if { [regexp {^Error} $line]}
{
puts $line
else {continue}
}

Q255. Why do only cell delays have aocv and not wire delays? (wire delays are flat derates , no aocv). How about wire delays? They depend on OPC etc right which is also random? (wire width variation based on OPC techniques like etching etc right. This etching process is not uniform across entire chip and that varies from one location to another depends on metal density in that area. That means as metal width is due to less etching and its width gets reduced if etching is excessive. wire delays will change from one place to other right? that means this is also random right?). Then why are we using flat derates?

Because cells have doping. which is affected by the process. AOCV is basically a function of both (Vt, doping) or process
Etching effect is taken care of by the nxgrd characterization, the etch values are tabulated in tluplus/nxtgrd (delays of wire changes w.r.t thickness, net length & temp etc)
Why are we applying flat derates or ocv for wires, why are we not applying aocv or variable derates?
Wire delays changes due to local process & temperature only (not due to voltage). If a timing path span over a huge distance, local temp of one net n2 might be different from the net n2 sitting in the different location (assume that thickness, net lengths in both locations are the same for nets n1 & n2). To address that issue, we have to use flat derates or OCV for wires

Q256. If you have an always on domain and a switching domain, where will you place the isolation cell?

In AON domain

Q257. What ae the components of Power?

Dynamic Power: Short circuit power, switching power due to external capacitance and switching power due to internal capacitors within the boundary of a cell Static or Leakage Power: Sub-Threshold Leakage current from drain to source when NMOS is at VSS, PMOS is at VDD, reverse saturation current through PN junction diodes formed b/w N-well & p-substrate, gate tunneling leakage current.

Q258. How can you reduce Dynamic power?

Techniques:

Multi-Supply Voltage or reduce supply voltage
- Multiple Frequencies or DVFS or reduce frequency
- Reduce switching activity on the nets
Reduce load or wire capacitance by minimizing the net lengths
Use place.coarse.icg_auto_bound command to place registers close to its driver ICG o Improve transitions on the nets
Use Decoupling Capacitors: It helps reduce power supply transients on the die and reduce dynamic or active power in the design, but it increases leakage power
Use clock gating, xor self-gating, power gating and multibit flops for addressing dynamic power
Area Recovery optimization: Downsize the drive strength of non-critical timing paths. So that their input pin cap will come down (CL is sum of wire cap, intrinsic capacitance of driver and input pin capacitances of fanout load). So dynamic power will reduce.
The tool optimizes the dynamic power by minimizing the net length of high switching nets to improve the power QoR if we give SAIF file (It has static probability & toggle rates for each signal net in the design, sdc will have toggle rate & static probability of clock nets) based on gate level or RTL simulation (or by annotating set_switching_activity on the design in the absence of SAIF file) by enabling power_low_power_placement and set_dynamic_optimization
Reduce unnecessary pessimism in setup/hold uncertainties (few people run a smaller number of timing scenarios by keeping huge uncertainty values) & use POCV (This will reduce the instance count and its internal short circuit power).
Use logic restructuring o Factoring High activity nets: Boolean factoring can be applied on a net with high activity to factor out the high activity net. This minimizes the number of logic fanouts for the high activity net.
Pin swapping: In certain cells, pins with equivalent functionality can have different input capacitances. In such cases, it is beneficial to move the high activity net to the pin with the lower capacitance.