Q241. STAR-RC & PT ECO Flow.
- StarRC command file for ECO Extraction for MW DB. MILKYWAY_DATABASE: CPU.mw
BLOCK: top_block_rev0
ECO_MODE: YES
STAR_DIRECTORY: star
NETLIST_FILE: pre_eco_full_chip.spef
NETLIST_ECO_FILE: post_eco_incr.spef
SUMMARY_FILE: pre_eco.star_sum
- Execute the StarRC run. The first run is a full-chip extraction and the resulting netlist is saved under the name specified by the NETLIST_FILEcommand. An empty netlist is saved to the file specified by the NETLIST_ECO_FILE command.
- Modify the read_parasitics command in the PrimeTime script to include both the full and ECO netlist names as follows:
read_parasitics -format spef -keep_capacitive_coupling \ ./pre_eco_full_chip.spef \
-eco ./post_eco_incr.spef
- Execute the PrimeTime run.
- Fix timing violations and save the changes in the design database
Q242. Do we perform dynamic/static IR drop analysis for all modes (functional, scan capture, scan shift)?
We take use case scenario of the chip which consumes dominant power. So we take that VCD and will close. there could be multiple VCD’s also in parallel.
Q243. In how many corners we will do IR drop analysis?
Dynamic power depends on “load capacitance” so we choose the corner (either rcworst or cworst corner) where impedance is more.
Q244. What is data toggle rate for static IR drop analysis/dynamic?
It is purely design dependent only. Use case scenario of VCD gives correct number
Q245. Does any relationship between dynamic IR drop target to static IR drop target? (Dynamic IR drop target < = 3*Static IR drop target).
Static works on average power basis and Dynamic works on peak/avg/rms current waveform basis analysis.
Q246. what is ramp up voltage? How will it vary? how to calculate? how it impacts the IR drop analysis?
ramp/wake up time: time it takes to bring voltage to its peak from 0 during system bring up time. In ramp up analysis flow we will get wake up time and voltage and how many cells are switching and not switching. If all the designs switch at one time, then demand will be more than supply and IR drop will be more so we prefer to connect all Power Switch cells in chain fashion and bring up them in serial manner.
Q247. off_state_leakage current? how will impact the IR drop?
by using header power switches, we can get relieved when they are in off state. If we are doing power gating, then there will be control on leakage current and hence leakage power in design so it automatically in control.
Q248. multi bit flip-flop designs pros & cons?
Replacing single-bit cells with multibit cells offers the following benefits:
- Reduction in area due to shared transistors and optimized transistor level layout.
- The area of the 2-bit cell is less than that of two 1-bit cells due to transistor-level optimization of the cell layout, which might include shared logic, shared power supply connections, and a shared substrate well. The register bits assigned to a bank must use the same clock signal and the same control signals, such as preset and clear signals.
- Reduction in the total length of the clock tree net.
- flip flops after merging reduces the dynamic power about 23.68% and the total power about 8.55% because lower net length. It is also found that the global clock buffer is reduced to 37.84%.
- Reduction in clock tree buffers and clock tree power
- This should also reduce clock skew in sequential gates as the clock paths are balanced internally in a whole multi-bit cell
- The SoC implementation using multi-bit flip-flops should result in smaller SoC area as the total number of clock buffers should reduce, resulting in less congestion.
- The multi-bit usage should improve the timing numbers, due to shared logic (in clock gating or set-reset logic) and an optimized multi-bit circuit and layout from library team.
Cons:
- IR Drop Issues
- EM Violations
- LEC difficulty as LEC done on comparing names. So u need to have svf file for mapping multibit fops to their single bit flops
Q249. Does jitter affect the hold violations?
Jitter is the time variation of a periodic signal. Since, we do check the hold violations on the same clock edge (launch and capture edge of the same flop), jitter will not affect the hold violations if there is no uncommon clock path. Jitter might affect hold if there is an uncommon path between the launch and capture clock (due to distribution jitter).
Q250. Does Jitter affect the setup violations?
Jitter affects the setup violations because we do check the setup violations on the clock edges of launch and capture flops.
