Q231. Pre & post-route correlation.
- At pre-route stage, interconnect RC delays are calculated with elmore delay engine by default (in ICC compiler) and at post-route stage, interconnect RC delays are calculated with Arnoldi delay engine. So we should check type of delay engines we are using at preroute stage. To get better correlation against post-route, we have to use AWE (Asymptotic Waveform Evaluation) delay engine at pre-route stage
- At pre-route stage, coupling caps were not considered and hence cross-talk effect was not present at the pre-route stage. Whereas in post-route stage, crosstalk affects came into the picture. So timing correlation issue will be there. Report timing for the same path from both route stage & post-cts optimize stage & see crosstalk is the main culprit for the bad correlation. If that is the case, then try to reduce the congestion for the design, you will see improved timing correlation
- Increase uncertainty value at post-cts stage & do post-cts optimization might improve correlation. But this kind of approach will over-optimize non-critical timing paths as well. It’s like unnecessarily adding overhead in terms of area by optimizing the non-critical timing paths. Before doing that, find out the timing violated paths at the route stage & increase uncertainty value if at all you see huge number of timing violations against post cts DB. If number of violated paths are very few, then see reasons for the violations. route all those timing critical nets with NDR or route with higher metal layers might help you to fix those violations
Q232. Post-route & Signoff timing correlation
- Prime-time always use Arnoldi delay engine for calculating interconnect RC delays. So for post-route designs, always turn-on Arnoldi engine to get the better timing correlation(ICC)
- Sometimes derates used in implementation tool are not consistent with the signoff PT. report timing for the same path from both PT & implementation tool with derates and then check for the derate consistency between both tools. If they don't match, then use proper derates at implementation tool for timing correlation.
- If you see miscorrelation by directly comparing timing path from IC Compiler (after extract_rc followed by report_timing) vs PrimeTime (read_parasitics followed by report_timing), try to narrow down the problem by reading the same parasitics file in IC Compiler and then find out the RC scaling factors from that. Using those new RC scaling factors might improve timing correlation.
- Report all the timing variables from the Signoff PT & compare them against the variables from implementation tool. Try to modify those variables in implementation tool for getting the better timing correlation. You will see the same variables b/w ICc & PT-SI, but we may not see similar variables in other implementation tools but we may find variables, which gives similar functionality as in PT.
- Implementation tool uses GBA (Graph Based Analysis - i.e. cell delay will be calculated based on the worst slew propagation through one of its input pins) by default. So this is more pessimistic approach. Whereas PT runs on both GBA & PBA (Path Base Analysis- cell delay will be calculated based on the actual propagation through the input pin). So change it to GBA if PT uses PBA. So that you will see better timing correlation
- In ICC, run check_signoff_correlation command to check the correlation between the IC Compiler & PrimeTime tools, and between the IC Compiler and StarRC tools including 1. The timing and signal integrity related variables, commands, and SDC setup in both the IC Compiler and PrimeTime tools 2. To check only the correlation between the IC Compiler and PrimeTime settings, use the check_primetime_icc_consistency_settings command instead of the check_signoff_correlation command
- Use same input data b/w ICC & PT like net list, SDC, reference libraries, operating conditions
Q233. ICC Vs Extraction Correlation
- Make sure that the same ITF file is used to generate TLUPlus and nxtgrd files (TLUPlus files will be used in ICC & nxtgrd files in StarRC)
- Make sure that both the. nxtgrd and TLUPlus files have been generated using the same grdgenxo version
- Pass the operating temperature information to StarRC using OPERATING_TEMPERATURE. o IC Compiler picks up this information automatically from the operating condition.
- Make sure that pin capacitance information is provided to StarRC o IC Compiler picks the pin capacitance information from the .db files StarRC takes the pin capacitance information from the .db files present in the LM view o If LM views are not present, specify pin capacitance information through SKIP_CELL_PORT_PROP_FILE in StarRC
- Turn OFF vIRtual shield extraction o set_extraction_options -vIRtual_shield_extraction false
- Ensure that the metal fill setting between IC Compiler and StarRC are consistent. The recommendation is to perform correlation without metal fill in both ICC and StarRC.
Q234. Draw NAND/ NOR gate using CMOS?
Q235. Why PMOS & NMOS in Transmission gate has always same area?
- Use of transistors as switches between driving circuits and load circuits are called transmission gates because switches can transmit information from one circuit to another.
- The bias applied to the transistor determines which terminal acts as the drain and which terminal acts as the source.
NMOS Transmission Gate:
NMOS gate connected to variable Vg & another terminal connected to load CL and another terminal will be connected to input voltage Vin. Output will be taken across load CL.
When Vin = Vdd
- If Vg= 0, then terminal with Vin=Vdd will acts as Drain & another terminal with load CL acts as source. So Vgs = 0 - 0 = 0 NMOS is off and V0 = 0
- Vs = Vdd - 0 = Vdd, so NMOS is ON (i.e. Vgs > Vt) and it starts charging load CL towards Vdd. charging will stop, once output reaches Vdd - Vt because voltage Vgs will become Vt at that time.
- So for Vin = Vdd, output will be Vdd - Vt, which was attenuated by Vt.
- This implies that output voltage never will be equal to VDD rather it will be lower by Vt
- This is one of the disadvantages of an NMOS transmission gate when Vin=Vdd.
When Vin = 0:
- The terminal with Vin=0 acts as source S & another terminal with load CL acts as drain D.
- If Vg = Vdd, then Vgs = Vdd - 0 = Vdd, so NMOS is ON (as Vgs > Vt ) and hence voltage across load CL will starts discharge through NMOS & source S.
- So output V0 = 0 when Vin = 0.
- This implies that the NMOS transistor provide a “good” logic 0 when Vin= 0
That’s why we will not use NMOS as transmission gate as it is producing output value of Vdd-Vt when Vin= Vdd
CMOS Transmission gate:
- A CMOS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals.
- The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation The advantage of using a complementary pair, rather than a single NMOS or PMOS device to realize a transmission gate is that the gate delay time is almost independent of the voltage level of the input variable of the CMOS transmission gate.
- The reason you would find a beta ratio equal to 1 in some instances is because, when the transmission gate is turned-on, both the PMOS and NMOS are turned on and are in parallel. Even though only the PMOS is good at passing '1' and NMOS is good at passing '0', they do pass the opposite logic level weakly. So, together the average resistance is lower than having only one MOS on. So, you don't really need a beta=2 like in an CMOs inverter but something like 1.5 or 1 is sufficient.
Q236. Explain CEL and FRAM view ?
CEL is the complete view of the design with all the layers (like GDS) FRAM is just the skeleton view of the design (like lef)
- CEL view: The full layout view of a physical structure such as a via, standard cell, macro, or whole chip; contains placement, routing, pin, and netlist information for the cell
- CEL view, which contains all of the cell information needed for placement, routing, and mask generation. This includes placement information such as tracks, site rows, and placement blockages; routing information such as netlist, pin, route guide, and interconnect modeling information, and all mask layer geometries, which are used for final mask generation.
- FRAM view: An abstract representation of a cell used for placement and routing; contains only the metal blockages, allowed via areas, and pins of the cell
- The FRAM view is an abstraction of the cell containing only the information needed for placement and routing: the metal blockage areas where routes are not allowed, the allowed via areas, and the pin locations. The process of creating a FRAM view from a CEL view is often called blockage, pin, and via (BPV) extraction.
- The FRAM view is used for placement and routing, whereas the CEL view is used only for generating the final stream of mask data for chip manufacturing.
Q237. what’s the reason behind tapping n-well to VDD & p-substrate to VSS?
To prevent forward biasing drain to n-well junction & source to p-substrate junction.
Q238. Well Edge Proximity (WEP) effect:
Transistors near the edge of a retrograde well (e.g., within about 1 nm) may have different threshold voltages than those far from the edge because ions scatter off the photoresist mask into the edge of the well. This is called the well-edge proximity effect.
Q239. Why Metal Density Rule needed?
We have to maintain minimum and maximum density of a particular layer within a specified area. Etch rates have some sensitivity to the amount of material that must be removed. For example, if polysilicon density were too high or too low, transistor gates might end up over- or under etched, resulting in channel-length variations. Similarly, the CMP process may cause dishing (excessive removal) of copper when the density is not uniform.
To prevent these issues, a metal layer might be required to have 30% minimum and 70% maximum density within a 100 m by 100 m area diffusion, polysilicon, and metal layers may have to be added manually or by a fill program after design has been completed. The fill can be grounded or left floating. Floating fill contributes lower total capacitance but more coupling capacitance to nearby wires. Grounded fill requires routing the ground net to the fill structures Metal fill can exist in a variety of shapes and sizes. Typically, there are two types of metal fill structures in a design: grounded metal fill and floating metal fill. Grounded metal fill is connected to power or ground by via connections; floating metal fill has no connection to signal, power, or ground nets. Both types might exist in the same layout.
When running StarRc extraction, you can specify the metal fill to be emulated or real. These two approaches yield different results depending on the accuracy requirements. However, emulation fill is used only during the early stages of the place-and-route flow and should not be used for correlation with the place-and-route flow.
LEF/DEF has two different forms of syntax for specifying metal fill. Floating metal fill polygons are specified in the “FILLS” section of the DEF file. If the fill polygons are tied to power and ground nets, they are specified in the SPECIALNETS section (part of special WIRing with SHAPE defined as FILLWIRE) for the power and ground nets.
Metal fill can be processed in two ways: as grounded metal fill or floating metal fill.
● Grounded metal fill
During signal net extraction, the fill polygons are treated just like a polygon belonging to a power and ground net. There is no special handling of these polygons during extraction.
● Floating metal fill
In this mode, capacitance is calculated between signal and fill polygons and between different fill polygons. After extraction, fill nodes are reduced on the fly and equivalent capacitance between signal nets and capacitance to ground for signal nets is calculated.
A metal fill is said to be floating if it is not connected to any circuit element in the net list. The electrical potential at fill nets is effectively determined by setting the charge on the fill net set to zero. Even though fill nets are not electrically connected, they can introduce capacitive coupling effects between other nets
Gate & Diffusion Capacitances:
Diffusion capacitance depends on the size of the source/drain region. Wider transistors have proportionally greater diffusion capacitance. Increasing channel length increases gate capacitance proportionally but does not affect diffusion capacitance.
Q240. Explain ECO Extraction.
- ECO extraction is the technique of performing extraction only on parts of a design that are different from a reference design
- StarRC ECO extraction flow greatly reduce the total runtime by performing extraction only on the nets that were changed as a result of ECO fixes. In this flow, the StarRC tool maintains two parasitic netlists: one for full-chip extraction and one for the nets affected by the ECO
- ECO extraction achieves the same extraction accuracy as full-chip extraction by intelligently selecting nets for re-extraction. In addition to the nets directly changed by the ECO, the tool selects neighboring nets depending on their coupling capacitance to the ECO nets.
- The COUPLE_TO_GROUND command should be set to NO in the ECO flow.
- Net E, the ECO net, is a net that is modified as part of a timing violation fix. Net A is coupled to net E; this type of net is a directly ECO-affected net. Net N is not coupled directly to net E, but is coupled to net A. This type of net is an indirectly ECO-affected net.
- The StarRC tool includes net E and net A, but not net N, in the ECO netlist (the file specified by the NETLIST_ECO_FILE command). The coupling capacitance between net A and net N appears as a dangling capacitance under net A in the ECO netlist. The PrimeTime tool can read the ECO netlist and adjust the coupling and total capacitance of net N accordingly.
- If you do LVT swapping on a cell, then the StarRC tool does not re-extract the connected wires or replace them in the netlist.
- Netlists from full-chip extractions are written to the file specified by the NETLIST_FILE command. Netlists from ECO extractions are written to the file specified by the NETLIST_ECO_FILE command.
- The ECO_MODE command controls ECO extraction. The options are YES, RESET, and NO (the default).
- The first StarRC run is always a full-chip extraction because a reference run must exist for ECO extractions. Subsequent StarRC runs can be either full-chip or ECO extractions, depending on the number of ECO-affected nets compared to the size of the design. The StarRC tool maintains a full netlist and an ECO netlist; the PrimeTime tool can read both netlists and use them appropriately.
- Netlists from full-chip extractions are written to the file specified by the NETLIST_FILE command. Netlists from ECO extractions are written to the file specified by the NETLIST_ECO_FILE command.
An ECO extraction is performed unless one of the following conditions applies:
- StarRC tool does not perform any extraction and does not update the netlists, If the design database does not have any logical or physical changes since the previous extraction.
- If the star directory is missing, the tool performs full-chip extraction due to the absence of a reference run.
