Q221. What happens to power and timing when clk transition is bad?
- Dynamic power (short circuit power will increase),
- Increase the clock cell delays. It will impact the timing depends on the location of this cell in the clock network
- Impact the performance of the design (operating frequency will come down)
- If clock transition is bad on CK pin of capture register, then library setup & hold time will increase. it will make setup & hold timing fixing complex.
Q222. What happens to setup and hold when clk transition is bad?
There are different points which we need to consider here.
- Case 1. If clock transition is bad on launch clock pin and clock transition is good on capture register clk, then clk to q delay of launch register will increase. So, it will reduce setup window. So, in this case setup will get worse and hold will be better.
- Case 2: if clock transition is bad on capture clk and good on launch clk pin, then this will increase capture path delay and worsen the setup library margin. Then you have to say good or bad for setup based on the combined effect of library setup margin plus capture path delay increase due to bad clk transition.
- Case 3: if there is a clock transition on clk inverters (other than ck pins of launch & capture registers), then different scenarios come into this here.
A. If there is a bad clock transition on common clock path, then it will affect both launch & capture paths in the same way. So, it will not affect either setup or hold violation.
B. If there is a bad transition on lunch clock path, then launch path gets delayed. So bad for setup and it's better for hold violation
C. If there is a bad transition on capture clock path, then capture clock path gets delayed. It’s good for setup & bad for hold timing.
Q223. Why mesh over regular CTS?
Better skew, lower latency, help in achieving higher performance or frequency, better timing closure
Q224. Will you place your clock gates near the sink or the root?
- For timing, placing ICG near the sinks is better to address enable timing of ICG., but power will be bad due to this.
- For power efficiency, placing ICG near the root is better power reduction, timing on Enable pin will be bad due to this
Q225. What is power gating?
Power gating is a technique to switch off the block when it is not doing any operations. So that it will save a lot of power. There are two types of power gating techniques available; One is header, implemented with PMOS will be used for disconnecting VDD from the block. Other one if footer, implemented with NMOS will be used for disconnecting VSS from the block
Q226. What is an isolation cell? How do you decide on using an AND gate or an OR gate to implement the isolation cell?
- Isolation cell is placed at an interface where signal crosses from switchable power domain to AON power domain & both are operating at the same voltage.
- Main purpose of placing isolation cell is for preventing unknown logic signal getting propagated from switchable power domain to AON domain when switchable power domain is OFF.
- Another reason is that, if you don’t insert isolation cell, then unknown logic will reach AON domain, causes a metastability issues (logic level between 0 & 1) and hence it dissipates short circuit power.
- AND gates with isolation control signal (which is 0) comes from power management block to block the unknown signal entering AON domain.
- OR gate with isolation control signal (which is 1) comes from power management block to block the unknown signal entering AON domain.
Q227. Sources of Clock Skew at pre-CTS?
In-die Process, Voltage, Temperature (PVT) variation
1. Different clock buffers with different channel lengths
2. Local drop in voltage leads to increased buffer delay
3. Hot spots lead to increased gate and wire delay
4. Device mismatch across die Clock Jitter
Q228. What is Jitter and their sources?
Clock jitter is the clock edge inaccuracy introduced by the clock signal generation circuitry w.r.t ideal clock. Clock jitter may be viewed as a statistical variation of the clock period or duty cycle.
Sources of clock jitter:
- Temporal power supply variations 1. Changing activity can alter supply voltage in different cycles affecting either the global or regional (local) clock buffers.
- PLL Jitter 1. Supply variation at PLL can affect oscillator frequency 2. PLL components do not have zero response time 3. Reference clock jitter being multiplied by the PLL 4. Global clock distribution may add jitter to PLL due to supply noise causing the feedback clock signal to seem to jitter.
- Wire coupling 1. Changing data can alter coupling in different cycles
- Dynamic De Skewing Circuitry
Q229. Difference between Clock buffer and regular buffer
- Clock buffers: pros: Equal rise & fall transition times due to equal on resistance for both PMOS & NMOS transistor. This can be achieved by increasing the width of PMOS by 2.5 times the width of NMOS.
- It maintains pulse width
- Clock buffer delay will be less than the regular buffer as regular buffer has 2.5 times resistance of the NMOS resistance. So rise time will be more for regular buffer- This is not true (refer spreadsheet below) clock buffer actually has more delay than a regular buffer.
- Cons: Area of clock buffer is higher than the regular one due to increased PMOS width i.e. area penalty Leakage current is more due to lower ON resistance of PMOS. Hence leakage power will be more with clock buffers.
Q230. what is Miller Effect?
- Internal physical structure of the CMOS inverter there will be an internal feedback capacitance between the output drain and the input gate called Cgd. According to the Miller theorem, Cgd appears at the input multiplied by the amplifier gain A +1 (i.e.Cgd(A+1)). This has the consequence of decreasing the maximum operating frequency of the amplifier compared with no Cgd. Then as said before Cgd can drastically limit the bandwidth of the amplifier.
- If the CMOS inverter is used as a logic gate, the transistors act as switches. In the on and off states they are in a quasi-static state and the effect of Cgd is negligible. In the transitions from the on to off and vice versa the inverter will be amplifying and the miller effect becomes pronounced leading to appreciable increase in the input capacitance. The consequence is slowing down the inverter transition and the propagation delay time increases.
- In conclusion, the MILLER effect of Cgd decreases the highest operating frequency of the CMOS inverter.
- We can reduce the Miller effect using Cascode connection (Common Source in series with common Gate). The Cascode improves input-output isolation (or reverse transmission) as there is no direct coupling from the output to input. This eliminates the Miller effect and thus contributes to a much higher bandwidth
- The device engineers can reduce this capacitance by reducing the overlap area between the gate and drain. That is to minimize technologically Cgd.
- The load cell/receiver is a high drive strength cell (single stage cells such as an inverter) and the output is lightly loaded (short net) such that the fast transition on the output couples back strongly to the input interconnect through the miller capacitance (similar to crosstalk) and causes a lot of distortion at the input signal like it delays the signal transition.
- So here Receiver acts as an aggressor driver even though there is not external cross-talk. Hence it affects the operating frequency of the cell.
