Q211. what is threshold voltage? How does it affect cell propagation delay?
Threshold voltage is the minimum voltage required to establish a channel b/w source and drain in a CMOS. Delay of a cell is inversely proportional to the threshold voltage.
Q212. What is Power aware placement?
Low-power placement tries to shorten the length of high-activity nets based on the available switching activity. Low power placement does not do any optimization, including resizing drivers. However, it is done concurrently with timing, power, DRC, and congestion optimization that resizes cells.
Q213. HVT vs ULVT scaling across corners, which one would you prefer to fix hold if the path is also setup critical?
Cell delay variations of HVT cells are higher across different PVT corners (for different operating voltages and different temperatures due to temperature inversion) compared to ULVT cells because of the huge variation in drive voltage Vgs-Vt . So i use ULVT for this purpose
Q214. How do you fix Dynamic voltage drop?
- Making the power grid more denser by adding additional power/ground straps to improve current conductivity.
- Cell padding: Add cell padding to the cells which are switching simultaneously to reduce the peak current demand from the power grid.
- Downsizing cells: decrease the drive strength of the cells in the non-critical timing paths to reduce the instantaneous current demand in the local hotspots or as a preventive measure, you can use set_clock_cell_spacing command for spreading clock cells (which are having more switching activity compared to data path cells). This is nothing but changing the timing window of non-critical timing path cells
- Inserting decap cells: Decap acts as a charging reservoIR that can supply current to the standard cells when there is a simultaneous switching of cells in the hot spot region. However, decaps are leaky and it will add to the leakage power in the design
- Splitting output capacitance: Amount of current drawn from the power grid is directly proportional to the output capacitance that’s being driven. Load splitting can reduce the peak current demand from the power grid. So dynamic IR drop will be addressed.
- Use MIM (Metal -Insulator – Metal) for stabilizing the power
Q215. What are the factors that affect Vt?
- VDD(VDS) - As the VDS increases, depletion region around drain will increases. Hence channel length will decrease. So Threshold voltage will change or comes down
- Substrate body voltage: As the substrate body potential increases from 0V, then threshold will decrease. Vt = Vt(sb=0) - K [ Sqrt ( Phy + Vt(sb) - sqrt (phy)]
- Channel Length: Threshold voltage changes proportional to channel length
- Gate oxide thickness: As the gate oxide thickness reduces, threshold voltage will reduce. For smaller Vgs voltage, channel will form if thickness is less
- Temperature: As the temperature increases, the threshold voltage will decrease. Vt(T) = Vt(Tr) - K(T-Tr); Tr => Room Temperature, Where K is a factor
- Doping concentration in channel: Threshold voltage decreases with increasing doping in channel
- Doping in substrate will increase VT (assume doping in P-type substrate of NMOS will increase VT)
Q216. What happens to Vt when Temp incr? why?
VT decreases with Increasing temperature. Vt(T) = Vt(Tr) - K(T-Tr); Tr => Room Temperature, Where K is a factor
217. What happens to mobility when Temp incr? Why?
As the temperature increases, mobility will decrease because increased temperature will induce more charge carries, which will collide with other charge carriers. This will reduce the mobility of the carriers.
Q218. Does mobility keep decreasing with increasing in Temp?
Yes
Q219. PMOS (holes) vs NMOS (electron) mobility?
Electrons mobility is always higher than holes mobility. Its 2 to 2.5 times faster
Q220. What does delay of a cell depend on?
Input slew, output load, input signal vector sequence, Multiple input switching (MIS), VT, Mobility, temperature, channel-length, VDD, gate oxide thickness,
