Q201. Why antenna violation come on signal net, but not on power net?
Power nets are not connected to gate
Q202.How you will fix half cycle path?
Hold fixing is easy with half cycle paths, Setup will be critical by half cycle path
Q203. What are the technique to fix cross talk?
Layer promotion, reduce net length, shielding, upsizing driver, adding buffer.
Q204. How body biasing affects the timing?
Threshold voltage Vt will decrease increasing body/substrate bias voltage. Hence device runs at faster and timing gets improved & setup timing closure is easier. More power consumption
Q205. Can we get 0 skew what is the problem?
If skew is 0, then all the flops will trigger at the same time. So power consumption will be more.
Q206. On a post signoff DB, if we increase the frequency, what will happen?
Timing windows for each of the timings arcs in the design will change if we increase the frequency. As a result, overlapping of timing windows may change and hence it may increase/decrease the crosstalk effects in the design.
Q207. does the noise glitch always impact my device functionality?
No it doesn’t always impact functionality unless it captured by flop. Yes if there is a noise bump or glitch on the clock or set/reset pins of flops, then it will impact the functionality of design.
Noise bump on the victim net gets propagated onto the output of fanout cells if noise bump height is greater than the noise threshold & noise bump width is greater than the delay of fanout cell. As long as this noise bump doesn’t gets propagated through combination cells, there are no issues and no functionality change. If this noise bump gets propagated and finally reach the D pin of the flop & captured by the register will change the functionality.
Q208. relationship between timing window and frequency of the design?
Timing window is nothing but, difference between max and min arrival times on any timing arc’s. Timing window’s arrival times will change if we change the frequency.
Q209. if you want to improve the performance which one you change in your design uncertainty or Frequency?
Frequency. If you increase uncertainty & close timing with that can’t guarantee the desired performance as it won’t address noise related issues. But changing frequency will change the crosstalk arrival windows and impact the timing a lot. So if we can close timing with that, we can guarantee desired frequency.
Q210. how do you improve dynamic power in your design without considering architectural Changes?
Multibit, clock gating, xor self-gating on ungated registers, power aware placement using SAIF, reduce insertion delay, don’t use huge uncertainty values unnecessarily etc.
