Physical Design Q&A

Q201. Why antenna violation come on signal net, but not on power net?

Power nets are not connected to gate

Q202.How you will fix half cycle path?

Hold fixing is easy with half cycle paths, Setup will be critical by half cycle path

Q203. What are the technique to fix cross talk?

Layer promotion, reduce net length, shielding, upsizing driver, adding buffer.

Q204. How body biasing affects the timing?

Threshold voltage Vt will decrease increasing body/substrate bias voltage. Hence device runs at faster and timing gets improved & setup timing closure is easier. More power consumption

Q205. Can we get 0 skew what is the problem?

If skew is 0, then all the flops will trigger at the same time. So power consumption will be more.

Q206. On a post signoff DB, if we increase the frequency, what will happen?

Timing windows for each of the timings arcs in the design will change if we increase the frequency. As a result, overlapping of timing windows may change and hence it may increase/decrease the crosstalk effects in the design.

Q207. does the noise glitch always impact my device functionality?

No it doesn’t always impact functionality unless it captured by flop. Yes if there is a noise bump or glitch on the clock or set/reset pins of flops, then it will impact the functionality of design.
Noise bump on the victim net gets propagated onto the output of fanout cells if noise bump height is greater than the noise threshold & noise bump width is greater than the delay of fanout cell. As long as this noise bump doesn’t gets propagated through combination cells, there are no issues and no functionality change. If this noise bump gets propagated and finally reach the D pin of the flop & captured by the register will change the functionality.

Q208. relationship between timing window and frequency of the design?

Timing window is nothing but, difference between max and min arrival times on any timing arc’s. Timing window’s arrival times will change if we change the frequency.

Q209. if you want to improve the performance which one you change in your design uncertainty or Frequency?

Frequency. If you increase uncertainty & close timing with that can’t guarantee the desired performance as it won’t address noise related issues. But changing frequency will change the crosstalk arrival windows and impact the timing a lot. So if we can close timing with that, we can guarantee desired frequency.

Q210. how do you improve dynamic power in your design without considering architectural Changes?

Multibit, clock gating, xor self-gating on ungated registers, power aware placement using SAIF, reduce insertion delay, don’t use huge uncertainty values unnecessarily etc.
  • What is synthesis?
  • Goals of synthesis
  • Synthesis Flow
  • Synthesis (input & output)
  • HDL file gen. & lib setup
  • Reading files
  • Design envi. Constraints
  • Compile
  • Generate Reports
  • Write files
Go To page
  • Netlist(.v or .vhd)
  • Constraints
  • Liberty Timing File(.lib or .db)
  • Library Exchange Format(LEF)
  • Technology Related files
  • TLU+ File
  • Milkyway Library
  • Power Specification File
  • Optimization Directives
  • Design Exchange Formats
  • Clock Tree Constraints/ Specification
  • IO Information File
Go To page
  • import design
  • sanity checks
  • partitioning (flat and hierarchy)
  • objectives of floorplan
  • Inputs of floorplan
  • Floorplan flowchart
  • Floorplan Techniques
  • Terminologies and definitions
  • Steps in FloorPlan
  • Utilization
  • IO Placement
  • Macro Placement
  • Macro Placement Tips
  • Blockages (soft,hard,partial)
  • Halo/keepout margin
  • Issues arises due to bad floor-plan)
  • FloorPlan Qualifications
  • FloorPlan Output
Go To page
  • levels of power distribution
  • Power Management
  • Powerplanning involves
  • Inputs of powerplan
  • Properties of ideal powerplan
  • Power Information
  • PowerPlan calculations
  • Sub-Block configuration
  • fullchip configuration
  • UPF Content
  • Isolation Cell
  • Level Shifters
  • Retention Registers
  • Power Switches
  • Types of Power dissipation
  • IR Drop
  • Electromigration
Go To page
  • Pre-Placement
  • Pre-Placement Optimization
  • Placement
  • Placement Objectives
  • Goals of Placement
  • Inputs of Placement
  • Checks Before placement
  • Placement Methods(Timing & Congestion)
  • Placement Steps
  • Placement Optimization
  • Placement Qualifications
  • Placement Outputs
Go To page
  • Pre-CTS Optimization
  • CTS
  • Diff b/w HFNS & CTS
  • Diff b/w Clock & normal buffer
  • CTS inputs
  • CTS Goals
  • Clock latency
  • Clock problems
  • Main concerns for Clock design
  • Clock Skew
  • Clock Jitter
  • CTS Pre requisites
  • CTS Objects
  • CTS Flow
  • Clock Tree Reference
  • Clock Tree Exceptions
  • CTS Algorithm
  • Analyze the Clock tree
  • Post CTS Optimization
  • CTS Outputs
Go To page
  • Importance of Routing as Technology Shrinks
  • Routing Objectives
  • Routing
  • Routing Inputs
  • Routing Goals
  • Routing constraints
  • Routing Flow
  • Trial/Global Routing
  • Track Assignment
  • Detail/Nano Routing
  • Grid based Routing
  • Routing Preferences
  • Post Routing Optimization
  • Filler Cell Insertion
  • Metal Fill
  • Spare Cells Tie-up/ Tie-down
Go To page
  • Diff b/w DTA & STA
  • Static Timing Analysis
  • main steps in STA
  • STA(input & output)
  • Timing Report
  • Clocked storage elements
  • Delays
  • Pins related to clock
  • Timing Arc
  • Timing Unate
  • Clock definitions in STA
  • Timing Paths
  • Timing Path Groups
  • Clock Latency
  • Insertion Delay
  • Clock Uncertainty
  • Clock Skew
  • Clock Jitter
  • Glitch
  • Pulse width
  • Duty Cycle
  • Transition/Slew
  • Asynchronous Path
  • Critical Path
  • Shortest Path
  • Clock Gating Path
  • Launch path
  • Arrival Path
  • Required Time
  • Common Path Pessimism(CPP/CRPR)
  • Slack
  • Setup and Hold time
  • Setup & hold time violations
  • Recovery Time
  • Removal Time
  • Recovery & Removal time violations
  • Single Cycle path
  • Multi Cycle Path
  • Half Cycle Path
  • False Path
  • Clock Domain Crossing(CDC)
  • Clock Domain Synchronization Scheme
  • Bottleneck Analysis
  • Multi-VT Cells(HVT LVT SVT)
  • Time Borrowing/Stealing
  • Types of STA (PBA GBA)
  • Diff b/w PBA & GBA
  • Block based STA & Path based STA
Go To page

  • Congestion Analysis
  • Routing Congestion Analysis
  • Placement Cong. Analysis
  • Routing Congestion causes
  • Congestion Fixes
  • Global & local cong.
  • Congestion Profiles
Go To page
  • Power Analysis
  • Leakeage Power
  • Switching Power
  • Short Circuit
  • Leakage/static Power
  • Static power Dissipation
  • Types of Static Leakage
  • Static Power Reduction Techniques
  • Dynamic/Switching Power
  • Dynamic Power calculation depends on
  • Types of Dynamic Power
  • Dynamic Power Reduction Techniques
Go To page
  • IR Drop Analysis
  • Types of IR Drop & their methodologies
  • IR Drop Reasons
  • IR Drop Robustness Checks
  • IR Drop Impacts
  • IR Drop Remedies
  • Ldi/dt Effects
Go To page

  • Design Parasitics
  • Latch-Up
  • Electrostatic Discharge(ESD)
  • Electromigration
  • Antenna Effect
  • Crosstalk
  • Soft Errors
  • Sef Heating
Go To page
  • Cells in PD
  • Standard Cells
  • ICG Cells
  • Well Taps
  • End Caps
  • Filler Cells
  • Decap Cells
  • ESD Clamp
  • Spare Cells
  • Tie Cells
  • Delay Cells
  • Metrology Cells
Go To page
  • IO Pads
  • Types of IO Pads
Go To page
  • Delay Calculation
  • Delay Models
  • Interconnect Delay Models
  • Cell Delay Models
Go To page
  • Engineering Change Order
  • Post Synthesis ECO
  • Post Route ECO
  • Post Silicon ECO
  • Metal Layer ECO Example
Go To page
  • std cell library types
  • Classification wrt density and Vth
Go To page

  • The Discontinuity
  • Discontinuity: Classification
  • DFM/DFY
  • Yield Classification
  • Why DFM/DFY?
  • DFM/DFY Solution
  • Wire Spreading
  • metal Fill
  • CAA
  • CMP Aware-Design
  • Redundant Via
  • RET
  • Litho Process Check(LPC)
  • Layout Dependent Effects
  • Resolution Enhancement Techniques
  • Types of RET
  • Optical Proximity Correction(OPC)
  • Scattering Bars
  • Multiple Patterning
  • Phase-shift Masking
  • Off-Axis Illumination
Go To page
  • Corners
  • Need for corner analysis
  • PVT Variations
  • Corner Analysis
  • PVT/RC Corners
  • Temperature Inversion
  • Cross Corner Analysis
  • Modes of Analysis
  • MC/MM Analysis
  • OCV
  • Derating
  • OCV Timing Checks
  • OCV Enhancements
  • AOCV
  • SSTA
  • CRPR/CPPR
Go To page
Copyright © 2021