Q191. What is a zero-bit retention flop?
All retention flops need isolation on its clock pin and reset pin. These isolations can be implemented either as a part of the retention flop or we can have a separate isolation cell connected to the CK/RST pin. The advantage with the first implementation is that it reduces the complexity. The second implementation consumes less area because we can have a common isolation cell for multiple retention flops. But it increases the complexity in implementation. This latter method is called zero-bit retention flops
Q192. Generally, explain the implementation methods for zero-bit retention flop?
Firstly, if there are any isolation cells in the incoming Netlist on the CK/RST pins of the retention flop we remove them. After the HFNS we take the last buffer connected to the reset pin of the retention flop and convert it into an iso high cell. This will take care of the reset pin isolation. Before CTS stage, we get all the fan-in of the CK pins of all the retention flops. These will be ICG outputs. On these outputs we will insert an isolation (iso low) cell. We add a don’t touch on the outputs of these isolation cells. Now we let the tool do CTS. During CTS the tool will clone the isolation cells as required. This will take care of the clock isolation.
Q193. What are the care about for retention flop secondary pin routing?
Throughout the design you would have a secondary power stripe in between the primary power stripes. During placement we would have to make sure all the RFFs are aligned with the secondary power stripes. This is to reduce the resistance of the RFF secondary power connections. Apply an attribute of route-as-signal on the secondary power pins of RFFs. Then we would apply an NDR of 3x width on these signal routed power nets. These will be routed before clock nets and signal nets.
Q194. What is the difference between a destination isolation cell and source isolation cell?
Isolation is required while crossing from a switchable domain to an AON domain. The isolation cell can be placed either in the switchable domain (source isolated) or the AON domain (destination isolated). If it is in the switchable domain (source isolated) it will require a secondary power of the AON domain.
Q195. When do we need level shifters?
Level shifters are required when there is significant (if is above the noise margin) voltage difference between the two domains.
Q196. What's the effect on setup and hold if we reduce the frequency (increasing the clock period)?
- It will improve setup timing for both full and half cycle timing paths
- It will not affect the hold if it is full clock cycle path (as launch and capture edges comes at the same time), but it improves the hold timing for half cycle paths as the capture comes half cycle prior to the launch clock.
Q197. Does hold depends on frequency?
- Hold doesn’t depend on frequency for full cycle timing paths (same reason as above)
- But hold depends on frequency for half cycle timing paths as the launch and capture edges comes at different times. Same reason above
Q198. What type of EM violations you addressed in your career?
- First i will try to increase W of metal and if it is congested then i will go to higher layer to get more room to increase the width of the metal.
- Increase more no. of via's if violation is on via's.
Q199. If I randomly pick one cell in my design, then what is the power that cell will have in static and in vector less IR drop analysis?
Static power works on avg power calculation algorithm and assumes everything is switching since power uniformly got distributed whereas vector IR analysis works on let’s say if toggling rate is 20% then probability is also 20% that particular cells is going to switch.
Q200. What is tie-high and tie-low cells and where it is used?
TIEH & TIEL cells are used to protect cells from ESD. cell input pins will get connected to TIEH/TIEL instead of connecting them to PG. If they are connected to directly to PG, cells are going to damage if there is a power supply fluctuation.
