No, we cannot place cells between the space of IO and core boundary because in between IO and core boundary power rings will be placed and we may see routing issues.

1. Congestion near Macro corners due to insufficient placement blockage.
   
2. Standard cell placement in narrow channels led to congestion.
   
3. Macros of same partition which are placed far apart can cause timing violation.
   
4. Macro placement or macro channels is not proper.
   
5. Placement blockages not given.
   
6. No Macro to Macro channel space given.
   
7. High cell density.
   
8. High local utilization.
   
9. High number of complex cells like AOI/OAI cells which has more pin count are placed together.
   
10. Placement of std cells near macros.
    
11. Logic optimization is not properly done.
    
12. Pin density is more on edge of block.
    
13. Buffers added too many while optimization.
    
14. IO ports are crisscrossed; it needs to be properly aligned in order.

End Cap cells:

1. These cells prevent the cell damage during fabrication.
   
2. Used for row connectivity and specifying row ending.
   
3. To avoid drain and source short.
   
4. These are used to address boundary N-Well issues for DRC cleanup.

Well Tap cells:

1. These are used to connect VDD and GND to substrate and N-Well respectively because it results in lesser drift to prevent latch-up.
   
2. If we keep well taps according to the specified distances, N-Well potential leads to proper electrical functioning.
   
3. To limit the resistance between power and ground connections to wells of the substrate.

De-cap Cells:

1. They are temporary capacitors which are added in the design between power and ground rails to counter the functional failure due to dynamic IR drop.
   
2. To avoid the flop which is far from the power source going into metastable state.

Filler Cells:

1. To fill the empty space and provide connectivity of N-wells and implant layers.

Double width and double space.
After PNR stage if u will get timing /crosstalk/noise violations which are difficult to fix at ECO stage we can try this NDR option at routing stage.

USAGE OF NDRs and Example:
When we are routing special nets like clock we would like to provide more width and more spacing for them. Instead of default of 1unit spacing and 1unit width specified in tech file; But NDR having double spacing and double width. When clocknet is routed using NDR it has better Signal integrity, lesser crosstalk, lesser noise, but we cannot increase the spacing and width because it effects the area of the chip.

Double spacing: It is used to avoid the crosstalk.
Double width: It is used to avoid the EM.

SETUP: Minimum time required for data stability before the clock edge.
HOLD: Minimum time required for data stability after the clock edge.

Yes, we will check setup in placement stage, where as we won’t bother about hold because clock is idea in placement stage.

A. Setup:

1. Upsizing the cells
   
2. Replace buffer with two inverters
   
3. HVT to LVT
   
4. If the net delay is more than break the net and insert the buffer
   
5. Pin swapping
   
6. Pulling the launch and pushing the capture
   
7. Cloning
   
   

B. Hold:

1. Inserting the buffers
   
2. Downsizing the cells
   
3. LVT to HVT
   
4. Pushing the launch and pulling the capture

report_timing –all violators

• Use HVT cells for timing paths having +ve slacks.
  
  
• Use LVT cells for timing paths having -ve slacks.
  
  
• HVT cells have a larger delay but less leakage. +ve slack in a design is not useful as having only some paths working faster will not help overall design. We are good if the slack is 0. In such cases give up the slack by using HVT cells but gain on power dissipation.
  
  
• LVT cells are very fast but very leaky. Limit the use of LVT cells to only those paths that have difficulty in closing time.

Electromigration (EM) refer to the phenomenon of movement of metal atoms due to momentum transfer from conducting electrons to metal atoms. Current conduction over a period of time in a metal route causes opens or shorts due to EM effect. EM effect cannot be avoided. In order to minimize its effect, we use wider wires so that even with EM effect wire stays wide enough to conduct over the lifetime of the IC.