Q181. What is +ve unateness, -ve unateness & non-unate? Do you see Unateness in library? do we see unateness in DFF? What kind of Unateness you will see for DFF?
+ve Unateness: A timing arc is said by +ve unate, if output signal direction is same as the input signal direction or output signal does not change : Examples - AND, OR
-ve Unateness: A timing arc is said to be -ve unate, if output signal direction is opposite to that of input signal direction or output signal does not change Examples : NOR, NAND, Inverter
Non-Unate: In a non-unate timing arc, the output transition cannot be determined solely from the direction of change of an input but also depends upon the state of the other inputs. Example: XOR
We will see unateness for each & every timing arc of every cell like below. For DFF has non-unateness for the timing arc CP ➜ Q as it not only depends on the CP transition, but also depends on the transition on D Pin. See below example
pin(Q) {
direction : output;
max_capacitance : 0.404;
function : "IQ";
timing() {
related_pin : "CP";
timing_sense : non_unate;
timing_type : rising_edge;
}
Q182. What is -ve lib values in library?
- The library hold margin value can be negative. Thus, a negative hold check implies that the data pin of the flip-flop can change ahead of the clock pin and still meet the hold time check.
- The library setup margin values of a flip-flop can also be negative. This means that at the pins of the flip-flop, the data can change after the clock pin and still meet the setup time check.
- Can both setup and hold be negative? No; for the setup and hold checks to be consistent, the sum of setup and hold values should be positive. Thus, if the setup (or hold) check contains negative values - the corresponding hold (or setup) should be sufficiently positive so that the setup plus hold value is a positive quantity
- For flip-flops, it is helpful to have a negative hold time on scan data input pins. This gives flexibility in terms of clock skew and can eliminate the need for almost all buffer insertion for fixing hold violations in scan mode
pin (D) {
direction : input;
timing () {
related_pin : "CK";
timing_type : "hold_rising";
rise_constraint ("setuphold_template_3x3") {
index_1("0.4, 0.57, 0.84"); /* Data transition */
index_2("0.4, 0.57, 0.84"); /* Clock transition */
values( /* 0.4 0.57 0.84 */ \
/* 0.4 */ "-0.220, -0.339, -0.584", \
/* 0.57 */ "-0.247, -0.381, -0.729", \
/* 0.84 */ "-0.398, -0.516, -0.864");}}
Q183. What is antenna violation & how do you fix it? what kind of antenna violations do you see in 28nm technology node? Why to fix accumulation area/gate area when foundry discharge all charge after each mask building?
- we will see 2 kinds of antenna violations in 28nm technology node.
- One is metal area/gate area
- 2nd one is cumulative metal area/gate area
- Because the Etching happens layer after layer, even if you have removed the charge after each lower layer there is still a chance that the small remains or develops again which when combined collectively can destroy the gate as at the lower technology nodes the gate length is very minimal and sensitive to slight charge build up.
- In accumulative area mode, the tool considers the metal segments on the current layer and all lower-layer segments. In this mode, the antenna ratio is calculated as
antenna_ratio = all connected metal areas / total gate area
Q184. how is nxtgrd file different from ICC TLUPlus file? why can't we use nxtgrd in ICC to match RC delays?
- Both nxtgrd & TLUPLus files are generated from same ITF file with grdgenxo utility in STARRC (with same type of version)
- Both files contain similar kind of RC interconnect related Info & cap tables. But files formats are different
- ICC extract engine (rc_extract) might not take the format inside the nxtgrd file
Q185. How do u reduce short ckt current for standalone inverter if no vdd/freq involved?
Short circuit current is large if output load capacitance is low and input rise/fall time is large.
To reduce short circuit power dissipation input/output rise and fall times should be of same order t
PAvg(short-circuit) = 1/12[k t f (VDD- Vthn -|Vthp|)3]
In general, short circuit current is proportional to frequency f ( i.e.short circuit current in general comes when clock changes from 0 to 1 or 1 to 0 . so if clock is toggling more due to clock frequency, then short circuit current will be more or vice versa) and voltage
Q186. What is die/scribe/sealer line/mask/die/corner cell?
Special corner cells are used to turn the power signals around the corners of shutdown block
Q187. Can we increase GRC cell size?
No user control in ICC for GRC size, it is dynamically calculated by tool and is not constant. By default, width of GRC is equal to the standard cell row height
Q188. What measures do you take for preventing SI issues in the design?
Placement
- reduce congestion in the design or do SI aware placement
- avoid higher cell density regions
- use place_opt –congestion –area_recovery command
- Don't use lower drive strength cells. It acts as a victim net
- Keep high driver strength cells in don’t use list. It will act as aggressor nets
- Help prevent crosstalk by controlling the maximum transition constraint defined on the design. The maximum transition constraint is technology and library dependent. You need to find the best tradeoff between a low maximum transition constraint and congestion. The maximum transition constraint can be relaxed during post route optimization.
- Use the maximum net length constraint in the IC Compiler tool to minimize the crosstalk effect by preventing very long wires
CTS
- Apply NDR rules for clock network. So that clock network would be less sensitive to crosstalk effects
- Apply spacing b/w clock network from signal nets
- Because clock nets are typically high-frequency nets, they are often strong aggressor nets. You can prevent crosstalk by shielding clock nets with ground wires.
- Try to avoid placing clock gators sitting very close by adding some padding to those gators. Because, they act as aggressors to the adjacent signal nets
Route
- Do SI aware routing or crosstalk aware detail route
- Route can perform the following signal integrity tasks
- Preventing crosstalk (during global routing and track assignment)
- Fixing crosstalk violations during post route optimization
Crosstalk prevention during track assignment:
Enable crosstalk prevention by running set_si_options -route_xtalk_prevention true and using the -xtalk_reduction option when you run route_opt
Q189. How will you identify what is the sign off requirement for static IR drop analysis? and dynamic drop analysis?
It comes from the top level, normally it will be 10-20% based on the SOC.
Static IR Drop: 2.5 to 3% of (VDD + VSS)
Dynamic IR Drop : 3x times the static IR drop
Q190. Do we have to consider timing margins in IR drop target?
Yes. it considers timing information. Redhawk takes the timing window file (which contains slew and load info on each pin) as input for better results. U can get more info in Redhawk manual.
