Q171. how do you get the options/default settings in EDI?
get*Mode, where * means ECO, trailRoute, detailRoute
Q172. how do you get llx & ury of a macro?
- set llx [lindex [lindex [dbGet [dbGet -p top.instance.name $macro].box] 0] 0]
- set lly [lindex [lindex [dbGet [dbGet -p top.instance.name $macro].box] 0] 1]
Q173. what’s the difference b/w regular OCV & AOCV? Do you think regular OCV derating factors are more pessimistic than AOCV?
- yes, Regular OCV is more pessimistic when we have deep logic level depth
- In regular OCV - flat derating are applied on all the cells Irrespective of the levels of logic and hence we will see huge number of timing violations
- AOCV: derating factors will decrease if the depth of the logic increases and derating will increase if distance of the cell from its diverging point
- A longer path that has more gates tends to have less total variation because the random variations from gate to gate tend to cancel each other out. Accordingly, advanced OCV applies higher derating values to short clock paths and lower derating values to long clock paths
- AOCV determines derating factors based on metrics of path logic depth and the physical distance traversed by a particular path. A longer path that has more gates tends to have less total variation because the random variations from gate to gate tend to cancel each other out. A path that spans a large physical distance across the chip tends to have larger systematic variations. AOCV is less pessimistic than a traditional OCV analysis, which relies on constant derating factors that do not take path-specific metrics into account.
Q174. what do you mean by "location based Derating" in AOCV? what's the reference which you take for deciding the derating number for a cell?
OCV derating will increasing with increasing location for the cell from diverging point in the clock
Q175. why can’t we route the design first and then do the clock tree synthesis? Any reasons?
- In general routing will be done based on timing driven & it will be possible only after clock is built.
- if the design gets routed first, then for clock tree you will not get proper routing resources and hence clock routing get de-tour & will impact insertion delay & skew
Q176. What happens if you swap PMOS & NMOS in CMOS inverter?
PMOS:
ON when V(gs) < -V(tp) & OFF when V(gs) > -V(tp)
NMOS:
ON when V(gs) > V(tn) & OFF when V(gs) < V(tp)
Assume V(tn)=V(tp)=V(t)
When PMOS & NMOS were swapped their positions, then connections will be like below
NMOS: Drain D connected to Vdd & Source S connected to load CL
PMOS: Drain D connected to Ground & Source S connected to load CL
Output voltage will take across CL and Assume initial voltage across CL is 0v
When Vin = Vdd:
For NMOS: V(gs) = Vdd - 0 = Vdd , which greater than V(t) and hence NMOS is on [i.e.V(gs) > V(t) ] and it starts charging the load capacitor CL towards Vdd.
When output voltage V0 across CL reaches Vdd - V(t) [i.e.V0 = Vdd - V(t)] , then voltage difference b/w gate & source of
NMOS will become come down to V(t) [i.e.Vgs = Vg - Vs = Vdd - (Vdd-V(t)) = V(t) ]. Then NMOS will be OFF.
So when Vin = Vdd, output V0 is Vdd-V(t). Output gets attenuated by V(t).
For PMOS: V(gs) = Vg - Vs = Vdd - 0 = Vdd , which is greater than -V(t) , so PMOs is OFF.
When Vin = 0
For NMOS: V(gs) = Vg - Vs = 0 - ( Vdd - V(t)) = - (Vdd - V(t)) , so NMOS is OFF
For PMOs: V(gs) = Vg - Vs = 0 - ( Vdd - V(t)) = - (Vdd - V(t) , which is less than -V(t) i.e.V(gs) < -V(t) condition is satisfying
. So PMOS is ON.
hence voltage across load Capacitor CL will starts discharging through PMOS towards 0v and it will stop discharging
when voltage across load CL reaches V(t). So at this point Vgs = Vg - Vs = 0 - V(t) = -Vt. So PMOS will be OFF at this point.
So output voltage across load CL will be V(t) when Vin is 0v.
Summary:
V0 = Vdd - V(t) when Vin = vdd
V0 = V(t) When Vin = 0v
So this circuit doesn’t acts as pure buffer, but acts as partial buffer
Q177. if Multi cycle value for hold is 2, then on which edge do you verify/check hold violation? and does this hold check depends on frequency?
Setup MCP will be checked against capture edge by default ( i.e.-end) and hold MCP will be checked against launch edge by default ( i.e.-start). Timing checks against edges will change based on the -start or -end options specified in MCP definition.
create_clock -name CLKM -period 10 [get_ports CLKM]
set_multicycle_path 3 -setup -from [get_pins UFF0/Q] -to [get_pins UFF1/D]
set_multicycle_path 2 -hold -from [get_pins UFF0/Q] -to [get_pins UFF1/D]
The setup multicycle constraint specifies that the path from UFF0/CK to UFF1/D can take up to three clock cycles to complete for a setup check.
A hold multi cycle of two is specified to get the same behavior of a hold check as in a single cycle setup case. This is because in the absence of such a hold multi cycle specification, the default hold check is done on the active edge prior to the setup capture edge which is not the intent. We need to move the hold check two cycles prior to the default hold check edge and hence a hold multi cycle of two is specified
The number of cycles denoted on a multicycle hold specifies how many clock cycles to move back from its default hold check edge (which is one active edge prior to the setup capture edge).
Since this path has a setup multi cycle of 3, its default hold check is on the active edge prior to the capture edge. In most designs, if the max path (or setup) requires N clock cycles, it is not feasible to achieve the min path constraint to be greater than (N-1) clock cycles. By specifying a multicycle hold of two cycles, the hold check edge is moved back to the launch edge (at 0ns)
Thus, in most designs, a multicycle setup specified as N (cycles) should be accompanied by a multicycle hold constraint specified as N-1 (cycles).
What happens when a multicycle setup of N is specified but the corresponding N-1 multicycle hold is missing? In such a case, the hold check is performed on the edge one cycle prior to the setup capture edge. For hold check, capture edge moved back to 0ns and launch edge is also at the 0ns, then hold doesn’t depends upon the frequency at all.
Q178. What is timing window & explain about it?
The STA obtains this information from the timing windows of the aggressor nets. During timing analysis, the earliest and the latest switching times of the nets are obtained. These times represent the timing windows during which a net may switch within a clock cycle. The switching windows (rising and falling) provide the necessary information on whether the aggressor nets can switch together.
Timing window : latest & earliest arrival times difference at a particular net is the timing window for that net. Timing window is the window, during which signal may change any time within clock cycle.
Q179. Why don't you fix peak power in dynamic and why do u fix only RMS power?
In DC circuits the power is always calculated as the RMS power which produces the same heating effect as the DC power.
The current drawn is always the rms current .... I=sqrt(Power/Resistance)
Q180. How to fix text short in LVS? Can we tapeout with text short? What exactly is text short?
Same net shape or pin shape or substrate layer with two different labels. (ideally speaking no risk as it is just a label short technically). But i will not tapeout as it can hide a case where two different nets with same label or indeed an open.
