Q161. There are 3 blocks with different voltage domains (assume V1,V2,V3) respectively.
V1 is “always on” , V2 is “ON/OFF(ONO Block)” and V3 is “shutdown” one.. V1 was placed at the top and V2 at the middle & V3 at the bottom.
How many isolation cells do u need if signal is going from V3 to V1 through V2?. and vice versa.
- Signal from V1-V3:
No isolation cell is needed when signal going from V1 to V2 as v1 is always on .
When V2 is off & V3 is on : 1 isolation cell needed b/w V2 & V3
when V2 is on & V3 is on : no isolation cell V2 & V3
- Signal from V3 -V1:
2 isolation cells are needed when signal passing from V3 to V1 . One e b/w V1 & V2 and another between V2 & V3.
For Better Understanding:
The power domain crossing scenarios for both AON and ONO are described in Figure below
Power domain crossing scenarios.
The cases for Figure are:
1. AON driving ONO (no isolation needed)
2. ONO driving ONO (no isolation needed)
3. ONO driving AON (isolation needed)
4. ONO feed through in ONO block
5. AON feed through in ONO block
Q162. How did you generate functional ECO with conformal LEC ?
generated functional ECO patch by comparing functional eco implemented synthesized netlist against the routed netlist with conformal.
Q163. what happens if I increase clock slew/transition during pre-cts stage?
- It’s for modeling clock to q delay and library setup check of the flop up front at the prects stage instead of waiting till CTS step.
- clock transition constraint on clock pins at the pre-cts stage is nothing but modeling library setup margin, which we see after cts.
- Library setup check on flops will increase (Library setup check will vary based on the slew on clock pin & slew on the data pin) and hence u will be having less available time period for the data path & Tool should work more hard to fix timing violations.
Q164. what happens if you have multiple clocks going through MUX? How do you build clock tree?
- We have to build "clock tree" for the functional clock going through D0 pin of MUX from its functional clock port to all the register pins
- Set_dont_touch_network on MUX/Z pin and then build CTS for test_clock
- Then fix "DRC only" clock tree on the Test clock connected to the D1 pin of MUX i.e. only up to D1 pin.
Q165. why do you focusing on clock skew instead of timing closure at the clock tree stage? i.e. why do u need to care of skew if my timing is met during CTS? why can’t you focus on timing instead of meeting skew at the CTS stage.
Reducing clock skew is not just a performance issue, it is also a manufacturing issue.
- Scan based testing, which is currently the most popular way to structurally test chips for manufacturing defects, requires minimum skew to allow the error free shifting of scan vectors to detect stuck-at and delay faults in a circuit.
- Hold failures at the best-case PVT Corner is common of these circuits since there are typically no logic gates between the output of one flop and the scan input on the next flop on the scan chain.
- Managing and reducing clock skew in this case often resolves these hold failures
Q166. There are 3 flops. setup time from A to B is +200ps and B to C is -50ps at pre-cts stage and skew constraints given was 50ps (i.e. A to B is 50ps skew & B to C is +50ps skew) at CTS stage. How will you fix it?
will borrow timing on either side i.e. early the clock pin of B flop by 50ps
Q167. At post route stage, If I have to over constrain the design slightly over, do u prefer adjusting the clock frequency or do u prefer adjusting clock uncertainty?
Adjusting clock frequency is always better because it changes/affects the calculation of crosstalk arrival windows. So that EDA tool can able to see these cross talks and fix it appropriately without over fixing the design & success rate is always higher on the silicon. Whereas if you change the uncertainty, it's not going to affect the calculation of cross talk arrival windows. I.e. you don’t see any increase in timing path violations due to crosstalk windows. But you do see huge number of timing path violations due to increase in uncertainty and you need to fix them blindly & it’s like over fixing the design. But there are chances that design will failure on the silicon & may not achieve the targeted performance because we may see cell delay changes/noise bumps due to crosstalk when we try to run the design at targeted/changed frequency.
Q168. If you adjust the clock uncertainty, does it affect the SI or not?
No. the clock uncertainty settings do not affect the calculation of crosstalk arrival windows.
Q169. If you adjust the clock frequency (clock period smaller), does it affect the SI or not?
Yes. change in the clock frequency will affect the calculation of cross talk arrival windows & crosstalk noise bumps if steady signal passes near the clock edge. As a result, delay of cross affected cells will change & pops up with more setup/hold violations. Tool will work on fixing these timing violations if there is a chance for optimization at route stage.
Q170. what are the top level commands used very frequently in EDI?
placeOpt , clockOpt, routeOpt, ecoRoute, ecoPlace, ...
