Q131. Why Metal Fill Insertion?
- Non uniform metal density causes problems during manufacturing
- Especially., Chemical mechanical polishing
- Extraction considering Metal fill environment
- Extraction does NOT consider metal fill in FILL view
- Extraction does NOT correctly consider fill in CELL view
- Timing analysis does NOT consider fill
Q132. Do you know about input vector controlled method of leakage reduction?
Leakage current of a gate is dependent on its inputs also. Hence find the set of inputs which gives least leakage. By applying this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.
Q133. How can you reduce dynamic power?
- Reduce switching activity by designing good RTL
- Clock gating
- Architectural improvements
- Reduce supply voltage
- Use multiple voltage domains-Multi vdd
Q134. What are the vectors of dynamic power?
Voltage and Current
Q135. What Is Partitioning?
- Partitioning is the process of splitting a design into manageable pieces. The purpose of partitioning is to divide complex design components into manageable pieces for ease of implementation. During this step, models for timing and physical implementation are defined. The floorplan defined during prototyping is pushed down into lower level blocks, thus preserving placement, power routing, and obstructions related to placement and routing. Feed-through might also be assigned for nets routed over-the-block and buffered by inserting hole-punch buffers or by modifying the block netlist Logical partitioning is not required for flat physical implementations.
- Partitioning splits design for logical and physical implementation. For hierarchical physical implementations, logical partitioning directly impacts the physical implementation phase.
- Partitioning is a method to manage functional complexity from a logical design perspective
- Partitioning allows multiple design teams to proceed in parallel
- The bridges between flat and hierarchical physical implementations are:
- Creation of timing budgets
- Pin optimization
- Feed-through or hole-punch buffer assignment
- Floorplan push-down (Obstructions, Power routes)
- Advanced netlist optimizations: timing, clock, power, and signal integrity
Q136. Compare the hierarchical and flattened design approaches related to ASIC design?
Flat Design
Advantages
- A flat design methodology ensures that there are no problems with boundary constraints between the different levels of hierarchy.
- You have the ability to analyze I/O and hard macro to block paths. You have more accurate timing analysis, because no block modeling is needed.
Disadvantages:
- Large data sizes
- Potentially long run
Hierarchical Design
Advantages:
- You can save time by closing timing at the top level and at the block level in parallel.
- Generate early top-level timing analysis.
- Smaller data sets lead to faster run times.
- You can reuse blocks once they are implemented.
- If the design uses an IP block, it is easier to insert it into a hierarchical modular design than to try and fit it into a flat design.
Disadvantages:
- Preliminary block characterization is inaccurate. and can yield false top and block-level timing violations as well as mask timing violations that appear to meet timing.
- You need to update block timing models frequently when the blocks change.
- Details are hidden or lost due to modeling at boundaries.
Q137. What parameters (or aspects) differentiate Chip Design and Block level design?
- Chip design has I/O pads; block design has pins.
- Chip design uses all metal layers available; block design may not use all metal layers.
- Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.
- Chip design requires several packaging; block design ends in a macro.
Q138. What are the Inputs needed for StarRC?
1. Milkyway or GDSII or LEF/DEF database
2. layer mapping file
3. nxtgrd file (contains RC interconnect info)
4. StarRC command file
5. StarXtract
GDSII layers for inclusion must be equated to a LEF database layer with the GDS_LAYER_MAP_FILE command. If any GDSII layer is not specified in the layer map file, it is not translated for extraction and does not contribute to the parasitics.
Q139. Which one do you prefer among PMOS & NMOs for power gating/power switches?
Header(PMOS):
- Higher resistance (due to lower mobility) and hence slew rate/transition will be more i.e. switching activity is slower
- short circuit power is more due to higher transition rate
- Leakage power will be less due to higher resistance - pros
- Switch ON & Switch OFF takes longer due to higher transition rate
Footer(NMOS):
- Lower resistance due to higher mobility & drive strength is more and hence slew rate will less
- Short circuit power is less due to lower transition rate
- leakage power will be more due to lower resistance
- Footer gates are smaller for the same amount of current (NMOS has twice the mobility of PMOS)
- Switch ON & Switch OFF takes less time due to lower transition rate
- We prefer PMOS header as it has less leakage (due to higher resistance) and slower switching rate. If switching rate is faster, it tries to draw huge rush current at the same time to switch on the block and it will cause the power integrity issue.
- Hence Power gating devices should be High VT cells for slower switching.
- NMOS is leakier than PMOS and Designs become more sensitive to ground noise on the vIRtual ground (VIRTUAL_VSS) coupled through the footer switch
- Selection of footer & header depends on the 3 parameters like switching efficiency, area efficiency & body bias
- Switch Efficiency: ratio of drain current in the ON and OFF states (Ion/Ioff). Total Leakage in the power switch is mainly determined by the switch efficiency.
- Area efficiency: depends on the product L*W. The switch efficiency decreases with the increase of W in pMOS transistors, therefore the small W is preferred.
- Body Bias: Applying reverse body bias on the sleep transistor can increase the switch efficiency (body bias increase Vt, as a result leakage current Ioff will be reduced) and reduce leakage significantly. Cost for the reverse body bias in the header switch is significantly smaller than in the footer switch. This is because NWELL for the PMOS is readily available for bias tapping in the standard CMOS process. Whereas nMOS transistor does not have a WELL in the standard CMOS process and its needs higher chip fabrication cost and design complexity
- Conclusion: pMOS header is preferable in reverse body bias application.
Q140. what is power gating, its integrity issues and compare coarse grain power gating with fine grain power gating?
Power Gating: Effective for reducing the leakage power in standby or sleep mode
Power Gating Overheads:
- Silicon area taken by the sleep transistors.
- Routing resources for permanent and virtual power networks.
- Complex power-gating design and implementation processes.
Power integrity issues.
- IR drop on the sleep transistors
- Ground bounce caused by inrush wake up current.
- Wakeup latency
Compared to fine grain, coarse grain power gating has
- Less sensitive to PVT variation
- Introduces less IR-drop variation
- Imposes a smaller area overhead
