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Physical Design Q&A

Q121. What is EM and it effects?

  • Due to high current flow in the metal atoms of the metal can displaced from its original place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.
  • Affects: Either short or open of the signal line or power line.

Q122. What does antenna rules signify related to ASIC backend? How are these violations handled?

  • In general, fixing antenna problems is quite expensive. Therefore, before fixing antenna violations, the routing should be completed with very few or 0 DRC violations.
  • Antenna fixing can be done either before or after 'Optimize Routing'. Running 'Optimize Routing' after antenna-fix can generate a good layout first. However, in most cases, running 'Optimize Routing' first can shorten the overall turn-around time if both steps are required.

Q123. What is Antenna effect and antenna ratio? How to eliminate this? why it occurs only in Deep sub-micron technology?

Antenna Ratio:
  • The antenna effect can occur during the chip manufacturing process and render a die useless. During metallization (when metal wires are laid across devices), some wires connected to the polysilicon gates of transistors may be left floating (unconnected) until the upper metal layers are deposited. A long floating interconnect can act as a temporary capacitor, collecting charges during fabrication steps, such as plasma etching. If the energy built-up on the floating node is suddenly discharged, the logic gate could suffer permanent damage due to transistor gate oxide breakdown. This is termed as Antenna Effect.
  • Because in nanotechnology the oxide thickness under the transistor gate is very thin. This problem was not there in 0.35u technology. Even if this charge does not get discharge to body. It stays in oxide as hot carrier. there by changing threshold, a big problem.


  • Antenna Elimination and its effect:


    Antenna Ratio:
    Antenna ratio is defined as the ratio between the physical area of the conductors making to the total gate oxide area to which the antenna is electrically connected. A higher ratio implies a greater propensity to fail due to the antenna effect.
    Antenna ratio for metal = 500
    Antenna ratio for metal = 1100

    Why Wire Spreading?

    • Random particle defects during manufacturing may cause shorts/opens on routes resulting in loss of yield
    • Such regions prune to shorts/opens are referred as ‘critical area’

    -To improve yield against the random particle Defects
    -Wire spreading resulting in more evenly distributed wire

    A probability distribution of various defect sizes to calculate critical area
    – The distribution function varies for different fabrication processes

    Push routes off-track by ½ pitch
    – May result in increase of “open” critical area even though reducing “short” critical area
    – Can choose to widen wires thus not increasing “open” critical area – Will not push the frozen nets

    Push routes off-track by ½ pitch where resulting length of the jog metal can be more than minimum jog length


    • Q124. Why NOT run wire spreading before Antenna fixing?

    • Not recommended, Antenna has the most priority after DRC
    • Wire spreading (by pushing off-track) might not leave enough resource to fix antenna

    Q125. Will wire spreading switch layers?

    • Pushes wires off the track if space available, doesn’t switch layers to allow pushing (spreading)
    • However, Search & Repair run after wire spreading may result in minimal changes to resolve DRC

    Q126. Will wire spreading introduce Antenna violations?

    • Antenna ratio dependent on Antenna length may change slightly by wire spreading
    • In most cases should NOT introduce new Antenna violations

    Q127. What/Why Double Via Insertion?

    • Voids in vias is a serious issue in manufacturing
    • To handle this issue,
    • Reduce via count: Optimize via techniques are employed in route_opt
    • Add backup vias: known as double vias

    Double via count
    Good : ~ 95% on all top level layers & ~70% on via1 Rolls back double via to avoid antenna violations

    DRC violations
    Double via introduces drc in congested designs

    Q128. Will double via increase critical area?

    Yes, any increase in metal (route/cut layer) on layout is bound to introduce critical area. But it will be very little.

    Q129. Will double via introduce new Antenna violations?

    • However, Search & Repair run later to resolve DRC might cause antenna violations
    • Turning ON antenna checking will roll back double to single vias reducing antennas

    Q130. Why Filler Cell Insertion?

    • For better yield, density of the chip needs to be uniform
    • Some placement sites remain empty on some Rows
      • Accepts two lists of filler cells: with/without metal
      • Cells without metal are inserted without checking drc’s You need to provide cells without any metal
      • Cells with metal are inserted only if no DRC violation Results

    • Filler cell Insertion
      • Inserts the cells in the order specified Larger to smaller is recommended
      • By default, honors the hard/soft placement blockages

    • What is synthesis?
    • Goals of synthesis
    • Synthesis Flow
    • Synthesis (input & output)
    • HDL file gen. & lib setup
    • Reading files
    • Design envi. Constraints
    • Compile
    • Generate Reports
    • Write files
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    • Netlist(.v or .vhd)
    • Constraints
    • Liberty Timing File(.lib or .db)
    • Library Exchange Format(LEF)
    • Technology Related files
    • TLU+ File
    • Milkyway Library
    • Power Specification File
    • Optimization Directives
    • Design Exchange Formats
    • Clock Tree Constraints/ Specification
    • IO Information File
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    • import design
    • sanity checks
    • partitioning (flat and hierarchy)
    • objectives of floorplan
    • Inputs of floorplan
    • Floorplan flowchart
    • Floorplan Techniques
    • Terminologies and definitions
    • Steps in FloorPlan
    • Utilization
    • IO Placement
    • Macro Placement
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    • Blockages (soft,hard,partial)
    • Halo/keepout margin
    • Issues arises due to bad floor-plan)
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    • levels of power distribution
    • Power Management
    • Powerplanning involves
    • Inputs of powerplan
    • Properties of ideal powerplan
    • Power Information
    • PowerPlan calculations
    • Sub-Block configuration
    • fullchip configuration
    • UPF Content
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    • Types of Power dissipation
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    • Pre-Placement
    • Pre-Placement Optimization
    • Placement
    • Placement Objectives
    • Goals of Placement
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    • Checks Before placement
    • Placement Methods(Timing & Congestion)
    • Placement Steps
    • Placement Optimization
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    • Pre-CTS Optimization
    • CTS
    • Diff b/w HFNS & CTS
    • Diff b/w Clock & normal buffer
    • CTS inputs
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    • Clock latency
    • Clock problems
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    • CTS Pre requisites
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    • Clock Tree Reference
    • Clock Tree Exceptions
    • CTS Algorithm
    • Analyze the Clock tree
    • Post CTS Optimization
    • CTS Outputs
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    • Importance of Routing as Technology Shrinks
    • Routing Objectives
    • Routing
    • Routing Inputs
    • Routing Goals
    • Routing constraints
    • Routing Flow
    • Trial/Global Routing
    • Track Assignment
    • Detail/Nano Routing
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    • Routing Preferences
    • Post Routing Optimization
    • Filler Cell Insertion
    • Metal Fill
    • Spare Cells Tie-up/ Tie-down
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    • Diff b/w DTA & STA
    • Static Timing Analysis
    • main steps in STA
    • STA(input & output)
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    • Clock definitions in STA
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    • Common Path Pessimism(CPP/CRPR)
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    • Single Cycle path
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    • Clock Domain Crossing(CDC)
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    • Bottleneck Analysis
    • Multi-VT Cells(HVT LVT SVT)
    • Time Borrowing/Stealing
    • Types of STA (PBA GBA)
    • Diff b/w PBA & GBA
    • Block based STA & Path based STA
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    • Congestion Analysis
    • Routing Congestion Analysis
    • Placement Cong. Analysis
    • Routing Congestion causes
    • Congestion Fixes
    • Global & local cong.
    • Congestion Profiles
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    • Power Analysis
    • Leakeage Power
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    • Leakage/static Power
    • Static power Dissipation
    • Types of Static Leakage
    • Static Power Reduction Techniques
    • Dynamic/Switching Power
    • Dynamic Power calculation depends on
    • Types of Dynamic Power
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    • IR Drop Analysis
    • Types of IR Drop & their methodologies
    • IR Drop Reasons
    • IR Drop Robustness Checks
    • IR Drop Impacts
    • IR Drop Remedies
    • Ldi/dt Effects
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    • Design Parasitics
    • Latch-Up
    • Electrostatic Discharge(ESD)
    • Electromigration
    • Antenna Effect
    • Crosstalk
    • Soft Errors
    • Sef Heating
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    • Cells in PD
    • Standard Cells
    • ICG Cells
    • Well Taps
    • End Caps
    • Filler Cells
    • Decap Cells
    • ESD Clamp
    • Spare Cells
    • Tie Cells
    • Delay Cells
    • Metrology Cells
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    • IO Pads
    • Types of IO Pads
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    • Delay Calculation
    • Delay Models
    • Interconnect Delay Models
    • Cell Delay Models
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    • Engineering Change Order
    • Post Synthesis ECO
    • Post Route ECO
    • Post Silicon ECO
    • Metal Layer ECO Example
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    • std cell library types
    • Classification wrt density and Vth
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    • The Discontinuity
    • Discontinuity: Classification
    • DFM/DFY
    • Yield Classification
    • Why DFM/DFY?
    • DFM/DFY Solution
    • Wire Spreading
    • metal Fill
    • CAA
    • CMP Aware-Design
    • Redundant Via
    • RET
    • Litho Process Check(LPC)
    • Layout Dependent Effects
    • Resolution Enhancement Techniques
    • Types of RET
    • Optical Proximity Correction(OPC)
    • Scattering Bars
    • Multiple Patterning
    • Phase-shift Masking
    • Off-Axis Illumination
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    • Corners
    • Need for corner analysis
    • PVT Variations
    • Corner Analysis
    • PVT/RC Corners
    • Temperature Inversion
    • Cross Corner Analysis
    • Modes of Analysis
    • MC/MM Analysis
    • OCV
    • Derating
    • OCV Timing Checks
    • OCV Enhancements
    • AOCV
    • SSTA
    • CRPR/CPPR
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