Backend (Physical Design) Interview Questions and Answers

Physical Design Q&A

Q101. Where do you get the WLM's? Do you create WLM's? How do you specify?

Wire Load Models (WLM) are available from the library vendors.
We don’t create WLM.
WLMs can be specified depending on the area

Q102. What is the derate value that can be used?

For setup check derate data path by 8% to 15%, no derate in the clock path.
For hold check derate clock path by 8% to 15%, no derate in the data path.

Q103. What are the corners you check for timing sign-off? Are there any changes in the derate value for each corner?

Corners: Worst, Best, Typical.
Same derating value for best and worst. For typical it can be less.

Q104. Write Setup and Hold equations?

Setup equation: Tlaunch + Tclk-q_max + Tcombo_max <= Tcapute + Tclk - Tsetup
Hold equation: Tlaunch + Tclk-q_min + Tcombo_min >= Tcapture + Thold

Q105. Where do you get the derating value? What are the factors that decide the derating factor?

Based on the guidelines and suggestions from the library vendor and previous design experience derating value is decided.
PVT variation is the factor that decides the derating factor.

Q106. What factors decides the setup time of flip-flop?

D- pin transition and clock transition.

Q107. Why don’t you derate the clock path by -10% for worst corner analysis?

We can do. But it may not be accurate as the data path derate.

Q108. What is latency? Give the types?

Source Latency

It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".
Delay from clock source to beginning of clock tree (i.e. clock definition point).
The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network latency

It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".
The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

Q109. What are the different types of delays in ASIC or VLSI design?

Different Types of Delays in ASIC or VLSI design

Source Delay/Latency
Network Delay/Latency
Insertion Delay
Transition Delay/Slew: Rise time, fall time
Path Delay
Net delay, wire delay, interconnect delay
Propagation Delay
Phase Delay
Cell Delay
Intrinsic Delay
Extrinsic Delay
Input Delay
Output Delay
Exit Delay
Latency (Pre/post CTS)
Uncertainty (Pre/Post CTS)
Unateness: Positive unateness, negative unateness
Jitter: PLL jitter, clock jitter

Gate delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]
Gate delay =function of(i/p transition time, Cnet+Cpin).
Cell delay is also same as Gate delay.

Source Delay (or Source Latency)

It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".
Delay from clock source to beginning of clock tree (i.e. clock definition point).
The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network Delay(latency)

It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".
The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

Insertion delay

The delay from the clock definition point to the clock pin of the register.

Transition delay

It is also known as "Slew". It is defined as the time taken to change the state of the signal. Time taken for the transition from logic 0 to logic 1 and vice versa. or Time taken by the input signal to rise from 10%(20%) to the 90%(80%) and vice versa.
Transition is the time it takes for the pin to change state.

Slew

Rate of change of logic. See Transition delay.
Slew rate is the speed of transition measured in volt / ns.

Rise Time

Rise time is the difference between the time when the signal crosses a low threshold to the time when the signal crosses the high threshold. It can be absolute or percent.
Low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level.

Fall Time

Fall time is the difference between the time when the signal crosses a high threshold to the time when the signal crosses the low threshold.
The low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level.
For an ideal square wave with 50% duty cycle, the rise time will be 0.For a symmetric triangular wave, this is reduced to just 50%.

Path delay

Path delay is also known as pin to pin delay. It is the delay from the input pin of the cell to the output pin of the cell.

Net Delay (or wire delay)

The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.
It is due to the finite resistance and capacitance of the net. It is also known as wire delay.
Wire delay =fn(Rnet , Cnet+Cpin)

Propagation delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.
This is the time required for a signal to propagate through a gate or net. For gates it is the time it takes for an event at the gate input to affect the gate output.
For net it is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net.
It is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2.

Phase delay

Same as insertion delay

Cell delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

Intrinsic delay

Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.
It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition. It is predominantly caused by the internal capacitance associated with its transistor.
This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

Extrinsic delay

Same as wire delay, net delay, interconnect delay, flight time.
Extrinsic delay is the delay effect that associated to with interconnect. output pin of the cell to the input pin of the next cell.

Input delay

Input delay is the time at which the data arrives at the input pin of the block from external circuit with respect to reference clock.

Output delay

Output delay is time required by the external circuit before which the data has to arrive at the output pin of the block with respect to reference clock.

Exit delay

It is defined as the delay in the longest path (critical path) between clock pad input and an output. It determines the maximum operating frequency of the design.

Latency (pre/post cts)

Latency is the summation of the Source latency and the Network latency. Pre CTS estimated latency will be considered during the synthesis and after CTS propagated latency is considered.

Uncertainty (pre/post cts)

Uncertainty is the amount of skew and the variation in the arrival clock edge. Pre CTS uncertainty is clock skew and clock Jitter. After CTS we can have some margin of skew + Jitter.

Unateness

A function is said to be unate if the rise transition on the positive unate input variable causes the output to rise or no change and vice versa.
Negative unateness means cell output logic is inverted version of input logic. eg. In inverter having input A and output Y, Y is -ve unate w.r.to A. Positive unate means cell output logic is same as that of input.
These +ve ad -ve unateness are constraints defined in library file and are defined for output pin w.r.to some input pin.
A clock signal is positive unate if a rising edge at the clock source can only cause a rising edge at the register clock pin, and a falling edge at the clock source can only cause a falling edge at the register clock pin.
A clock signal is negative unateness if a rising edge at the clock source can only cause a falling edge at the register clock pin, and a falling edge at the clock source can only cause a rising edge at the register clock pin. In other words, the clock signal is inverted.
A clock signal is not unate if the clock sense is ambiguous as a result of non-unate timing arcs in the clock path. For example, a clock that passes through an XOR gate is not unate because there are nonunate arcs in the gate. The clock sense could be either positive or negative, depending on the state of the other input to the XOR gate.

Jitter

The short-term variations of a signal with respect to its ideal position in time.
Jitter is the variation of the clock period from edge to edge. It can varry +/- jitter value.
From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. This can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform.

Sources of Jitter