Input data Required for Physical Design.

1. Technology file (.tf in synopsys format and .techlef in cadence format) : It describes the units, drawing patterns, layers design rules, vias, and parasitics resistance and capacitance of the manufacturing process.
   
2. Physical Libraries (In general Lef of GDS file for all design elements like macro, std Cell, IO pads etc., and in synopsys format .CEL, .FRAM views for the above) : Contains complete layout information and Abstract model for placement and routing like pin accessibility, blockages etc.
   
3. Timing, Logical and Power Libraries (.lib or LM view -.db for all design elements) : Contains Timing and Power info.
   
4. TDF file (.tdf or .io) : Contains pad or pin arrangements like order and location of the same. For full chip the instantiation of VDD and VSS pads Power Cut diode etc., (Whichever is not available in verilog netlist).
   
5. Constraints (.sdc) : Contain all design related constraints like Area, power, timing.
   
6. Physical Design Exchange Format –PDEF (optional) : Contains, row, cell placement locations etc.
   
7. Design Exchange Format –DEF (optional) : Contains, row, cell placement locations etc.

to know the input files in detail Click here

Output data from Physical Design Tool.

1. Standard delay format (.sdf) : Timing Details (Except load info).
   
   
2. Parasitic format (.spef, .dspf) : Resistance and Capacitance info of cells and nets.
   
   
3. Post routed Netlist (.v) Can be of flattened or hierarchical : Contains connectivity info of all cells.
   
   
4. Physical Layout (.gds) : Physical Layout info.
   
   
5. Design Exchange format (.def) : Contains, row, cell, net placement locations etc.,.
   
   

• Sanity Checks mainly checks the quality of netlist in terms of timing
  
• It also consists of checking the issues related to Library files, Timing Constraints, IOs and Optimization Directives
  
• Some of the Netlist Sanity Checks:
  
  1. Floating Pins
     
  2. Unconstrained Pins
     
  3. Un-driven i/p Ports
     
  4. Unloaded o/p Ports
     
  5. Pin direction mismatches
     
  6. Multiple drivers etc.
• Other possible issues include Unconnected/ Wrongly Connected Tie-high/ Tie-low Pins and Power Pins (since Tie-up or Tie-down connectivity always through Tie-Cells)

To start a floor plan first we need inputs like. v, .lib, .lef, .SDC This is the first major step in getting your layout done. Your floor plan determines your chip quality. At this step, you define the size of your chip/block, allocates power routing resources, place the hard macros, and reserve space for standard cells.

Flat

• Small to Medium ASIC
  
• Better Area Usage Since no reserve space around each sub-design for power/ground

Hierarchical

• For very large design
  
• When sub-systems are design individually
  
• Possible only if a design hierarchy exist

• Place macros around chip periphery: If you don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip periphery. Placing a macro inside the core can invite serious consequence during routing due to a lot of detour routing, because macros are equal to a large obstacle for routing. Another advantage to placing the hard macros around the core periphery is it's easier to supply power to them, and reduces the change of IR drop problems to macros consuming high amounts of power.
  
  
• Consider connections to fixed cells when placing macros: When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and preplaced macros. Place macros near their associate fixed element. Check connections by displaying flight lines in the GUI.
  
  
• Orient macros to minimize distance between pins: When you decide the orientation of macros, you also have to take account of pins positions and their connections.
  
  
• Reserve enough room around macros: For regular net routing and power grid, you have to reserve enough routing space around macros. In this case estimating routing resources with precision is very important. Use the congestion map from trial Route to identify hot spots between macros and adjust their placement as needed.
  
  
• Reduce open fields as much as possible: Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different aspect ratio (if that option is available) can eliminate open fields.
  
  
• Reserve space for power grid: The number of power routes required can change based on power consumption. You have to estimate the power consumption and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems.

Actually top level chip will be divided into some blocks, IO pins will be placed according to the communication between surrounding blocks. If we assign pins to left and right rather than top and bottom we will face routing issues in further stages.

channel spacing= no of pins*pitch/ (total number of metal layers/2)

There are two cases

1. If two macros communicating only with each other we can abutment the macros
   
2. If the macros communicating with other cells (std cells and IO ports) then we must should provide a proper channel spacing between the macros or else, we can see the routing issue

It depends on which technology you are working on. 45nm & below there are orientation requirements by foundry. Poly orientation should be same throughout the chip. So Macro poly orientation should match with the poly orientation of the standard cells.

For rings and stripes we use top metal layers because for top metal layers we have low resistivity.