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- Q1. What are the inputs required for any physical design tool and the outputs generated from the same?
- Q2. What you know about sanity checks?
- Q3. What we need to start Floor plan?
- Q4. Styles of PD Implementation?
- Q5. What are the guidelines to place macros?
- Q6. what happens if pins assign to left and right. (if you have IO pins at top and bottom)?
- Q7. How we will assign spacing between two macros?
- Q8. if we do macro abutment, what happens?
- Q9. Can we place macros 90 and 270 degees orientation?
- Q10. In power planning for rings and stripes which metal layers used and why?
- Q11. Can we place cells between the space of IO and core boundary?
- Q12. what type of congestion you've seen after placement?
- Q13. what are the physical cells?
- Q14. Tell about Non Default Rules?
- Q15. What is setup and hold?
- Q16. Can we do setup check at placement?
- Q17. What are all the fixing methods for setup and hold violations?
- Q18. How do you know you have max cap violation?
- Q19. How Do You Reduce Power Dissipation Using High Vt And Low Vt On Your Design?
- Q20. What Is Electromigration and How to Fix It?
- Q21. What Is The Importance Of IR Drop Analysis?
- Q22. If You Have Both Ir Drop And Congestion How Will You Fix It?
- Q23. In A Reg to Reg Path If You Have Setup Problem Where Will You Insert Buffer-near to Launching Flop or Capture Flop? Why?
- Q24. Why Buffers Are Used In Clock Tree?
- Q25. What Is Cross Talk?
- Q26. How Can You Avoid Cross Talk?
- Q27. How Shielding Avoids Crosstalk Problem? What Exactly Happens There?
- Q28. How Spacing Helps In Reducing Crosstalk Noise?
- Q29. How Buffer Can Be Used In Victim To Avoid Crosstalk?
- Q30. Why Setup is checked at max corner and Hold at min corner?
- Q31. Why we are not checking the hold before CTS?
- Q32. Can both Setup and Hold violations occur in same start and end points?
- Q33. What is the derate value that can be used?
- Q34. What are the corners you check for timing sign-off? Is there any changes in the derate value for each corner?
- Q35. Where do you get the WLM's? Do you create WLM's? How do you specify?
- Q36. Where do you get the derating value? What are the factors that decide the derating factor?
- Q37. Setup Fixes during placement and Setup and hold fixes during CTS?
- Q38. Why dont you derate the clock path by -10% for worst corner analysis?
- Q39. What are the importance and need of an MMMC file in VLSI physical design?
- Q40. What are Timing DRV/'s, explain the Causes and its fixes?
- Q41. Why do we emphasize on setup violation before CTS and hold violation after CTS?
- Q42. What should we do if there is a setup violation after placements even though we completed the optimization?
- Q43. What is meant by insertion delay in VLSI physical design?
- Q44. Why don't we do routing before CTS in VLSI Physical Design?
- Q45. What is a path group in VLSI, and why is it done?
- Q46. What is the benefit of having separate path groups for I/O logic paths in VLSI?
- Q47. While fixing timing, how do I find a false path in VLSI design?
- Q48. What makes meeting timing on clock gating paths very challenging? What makes it more critical than a regular setup/hold flop to flop timing path ?
- Q49. What is the difference between a static IR drop and a dynamic IR drop analysis?
- Q50. What is the need of Static IR drop analysis?
- Q51. What is GDSII file?
- Q52. What is a SDF file related to VLSI Physical Design?
- Q53. What is DEF file in VLSI?
- Q54. Explain the types of metal programmable ECO cells?
- Q55. What is +ve unateness ,-ve unateness & non-unate ?
- Q56. Can we get 0 skew what is the problem?
- Q57. what's the impact on the timing if you insert inverter on the capture clock pin?
- Q58. Difference between clock skew and clock latency?
- Q59. What is Pad limited design and core limited design. Is there any difference in approaches to handle these?
- Q60. How will we decide chip core area?
- Q61. How to arrive at the value of utilization factor and aspect ratio during initial floorplan?
- Q62. What is an HALO? How is it different from the blockage?
- Q63. How much utilization is used in the design?
- Q64. What is the difference between standard cells and IO cells? Is there any difference in their operating voltages? If so why is it?
- Q65. What is the significance of simultaneous switching output (SSO) file?
- Q66. Is there any checklist to be received from the front end related to switching activity of any nets to be taken care of at the floorplanning stage?
- Q67. What is power trunk ?
- Q68. How to handle hotspot in an chip?
- Q69. What is power gating?
- Q70. Whether macro power ring is mandatory or optional?
- Q71. If you have both IR drop and congestion how will you fix it?
- Q72. Is increasing power line width and providing more number of straps are the only solution to IR drop?
- Q73. what is tie-high and tie-low cells and where it is used?
- Q74. What are the placement optimization methods are used in SOCE and Astro Tool Design?
- Q75. What is Scan chain reordering? How will it impact Physical Design?
- Q76. In scan chains if some flip flops are +ve edge triggered and remaining flip flops are -ve edge triggered how it behaves?
- Q77. What you mean by scan chain reordering?
- Q78. What is JTAG?
- Q79. What is CTS?
- Q80. What are the SDC constraints associated with Clock tree?
- Q81. How are the number of Buffer (logic) levels determined during CTS?
- Q82. Which is better compared to buffer and inverter? If so, Why?
- Q83. While Doing CTS which buffer and inverters are used in the Design?
- Q84. How will you built Clock tree for Gated Clocks?
- Q85. Explain Clock tree Options for building better Clock Tree?
- Q86. How does a skew group relate to the clock phase and skew phase?
- Q87. Why to reduce Clock Skew?
- Q88. What are all the Checks to be done before doing CTS?
- Q89. How will you synthesize clock tree?
- Q90. How many clocks were there in this project?
- Q91. How did you handle all those clocks?
- Q92. Why buffers are used in clock tree?
- Q93. Which is more complicated when u have a 48 MHz and 500 MHz clock design?
- Q94. What is congestion?
- Q95. What kinds of timing violations are in a typical timing analysis report?
- Q96. Can a latch based design be analyzed using STA?
- Q97. How delays vary with different PVT conditions? Show the graph?
- Q98. What is cell delay and net delay?
- Q99. What are delay models and what is the difference between them?
- Q100. What is wire load model?
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- Q101. Where do you get the WLM's? Do you create WLM's? How do you specify?
- Q102. What is the derate value that can be used?
- Q103. What are the corners you check for timing sign-off? Is there any changes in the derate value for each corner?
- Q104. Write Setup and Hold equations?
- Q105. Where do you get the derating value? What are the factors that decide the derating factor?
- Q106. What factors decides the setup time of flip-flop?
- Q107. Why dont you derate the clock path by -10% for worst corner analysis?
- Q108. What is latency? Give the types?
- Q109. What are the different types of delays in ASIC or VLSI design?
- Q110. What are the violations are solved in DRC?
- Q111. What is the Difference between Magma and Caliber for solving the Problem of DRC LVS?
- Q112. In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why?
- Q113. What are the violations solved in LVS?
- Q114. During power analysis, if you are facing IR drop problem, then how did you avoid?
- Q115. What is cross talk?
- Q116. How can you avoid cross talk?
- Q117. How shielding avoids crosstalk problem? What exactly happens there?
- Q118. How spacing helps in reducing crosstalk noise?
- Q119. Why double spacing and multiple vias are used related to clock?
- Q120. How buffer can be used in victim to avoid crosstalk?
- Q121. What is EM and it effects?
- Q122. What does antenna rules signify related to ASIC backend?How are these violations handled?
- Q123. What is Antenna effect and antenna ratio? How to eliminate this? why it occurs only in Deep sub-micron technology?
- Q124. Why NOT run wire spreading before Antenna fixing?
- Q125. Will wire spreading switch layers?
- Q126. Will wire spreading introduce Antenna violations?
- Q127. What/Why Double Via Insertion?
- Q128. Will double via increase critical area?
- Q129. Will double via introduce new Antenna violations?
- Q130. Why Filler Cell Insertion?
- Q131. Why Metal Fill Insertion?
- Q132. Do you know about input vector controlled method of leakage reduction?
- Q133. How can you reduce dynamic power?
- Q134. What are the vectors of dynamic power?
- Q135. What Is Partitioning?
- Q136. Compare the hierarchical and flattened design approaches related to ASIC design?
- Q137. What parameters (or aspects) differentiate Chip Design and Block level design?
- Q138. What are the Inputs needed for StarRC?
- Q139. Which one do you prefer among PMOS & NMOs for power gating/power switches?
- Q140. what is power gating, its integrity issues and compare coarse grain power gating with fine grain power gating?
- Q141. After clock tree synthesis (CTS), many timing paths that end at clock gate/ICG enable pins appear. Why didn't these paths get fixed in placement, and how can I handle them?
- Q142. How CRPR should be treated in SI Analysis? i.e. Will you keep/remove pessimism from crosstalk affected cells during setup analysis using SI or crosstalk analysis? why?
- Q143. Why do we have different uncertainties for setup & hold at pre-cts & post-cts? what's the reason?
- Q144. why do we have different de-rating factors for clock cells & data cells? what's the reason for that?
- Q145. what are the pros & cons when u use buffers & Inverters for CTS? which one do you prefer for CTS?
- Q146. Whats the purpose of TIE cells & whats the internal struture of the TIE?
- Q147. why are we using clock uncertainties (setup uncertainty & hold uncertainty) after post-cts stage if we use OCV derating factors?
- Q148. How do you fix setup timing violation if base gets frozen?
- Q149. What are the ways to fix antenna violations?
- Q150. Can net delay become reduce if you split net by adding buffer?
- Q151. Why can’t we use PMOS as footer & NMOS as header?
- Q152. Tell me about NLDM Vs CCS?
- Q153. How do you fix DRC’s in particular area on routed database, which is going to get tape-out soon? consider two cases like cell density is higher & lower in that area?
- Q154. how do you fix congestion in particular area ( core area) during pre-cts stage?
- Q155. There are 10 macros & they should be placed in 5x2 (10 macros should be placed in 2 columns) array. How much vertical channel you will leave for routing all the macro pins?
- Q156. what's the impact on the timing if you insert inverter on the capture clock pin?
- Q157. Will you remove CRPR on setup half cycle timing paths & hold half cycle timing paths in the presence of cross talk? (i.e. when you insert inverter on capture clock pin)?
- Q158. how do you improve insertion delay?
- Q159. How do you fix Antenna violations? What are the possible methods for fixing those violations?
- Q160. Can you fix antenna violation with buffer?
- Q161. There are 3 blocks with different voltage domains (assume V1,V2,V3) respectively.
V1 is “always on” , V2 is “less always on than V1” and V3 is “shutdown” one.. V1 was placed at the top and V2 at the middle & V3 at the bottom.
How many isolation cells do u need if signal is going from V3 to V1 through V2?. and vice versa?
- Q162. How did you generate functional ECO with conformal LEC & how big is the functional ECO?
- Q163. what happens if I increase clock slew/transition during pre-cts stage?
- Q164. what happens if u have multiple clocks going through MUX? How do you build clock tree?
- Q165. why do u focusing on clock skew instead of timing closure at the clock tree stage? i.e. why do u need to care of skew if my timing is met during CTS? why can’t you focus on timing instead of meeting skew at the CTS stage?
- Q166. There are 3 flops. setup time from A to B is +200ps and B to C is -50ps at pre-cts stage and skew constraints given was 50ps (i.e. A to B is 50ps skew & B to C is +50ps skew) at CTS stage. How will you fix it?
- Q167. At post route stage, If I have to over constrain the design slightly over , do u prefer adjusting the clock frequency or do u prefer adjusting clock uncertainty?
- Q168. If you adjust the clock uncertainty, does it affect the SI or not?
- Q169. If you adjust the clock frequency (clock period smaller), does it affect the SI or not?
- Q170. what are the top level commands used very frequently in EDI?
- Q171. how do you get the options/default settings in EDI?
- Q172. how do you get llx & ury of a macro?
- Q173. whats the difference b/w regular OCV & AOCV?. Do you think regular OCV derating factors are more pessimistic than AOCV?
- Q174. what do you mean by "location based Derating" in AOCV?. what's the reference which you take for deciding the derating number for a cell?
- Q175. why can’t we route the design first and then do the clock tree synthesis? Any reasons?
- Q176. What happens if you swap PMOS & NMOS in CMOS inverter ?
- Q177. if Multi cycle value for hold is 2 , then on which edge do you verify/check hold violation? and does this hold check depends on frequency ?
- Q178. What is timing window & explain about it?
- Q179. Why don't you fix peak power in dynamic and why do u fix only RMS power?
- Q180. How to fix text short in LVS? Can we tapeout with text short? What exactly is text short?
- Q181. What is +ve unateness, -ve unateness & non-unate? Do you see Unateness in library? do we see unateness in DFF? What kind of Unateness you will see for DFF?
- Q182. What is -ve lib values in library?
- Q183. What is antenna violation & how do you fix it? what kind of antenna violations do you see in 28nm technology node? Why to fix accumulation area/gate area when foundry discharge all charge after each mask building?
- Q184. how is nxtgrd file different from ICC TLUPlus file? why can't we use nxtgrd in ICC to match RC delays?
- Q185. How do u reduce short ckt current for standalone inverter if no vdd/freq involved?
- Q186. What is die/scribe/sealer line/mask/die/corner cell?
- Q187. Can we increase GRC cell size?
- Q188. What measures do you take for preventing SI issues in the design?
- Q189. How will you identify what is the sign off requirement for static ir drop analysis? and dynamic drop analysis?
- Q190. Do we have to consider timing margins in ir drop target?
- Q191. What is a zero-bit retention flop?
- Q192. Generally, explain the implementation methods for zero-bit retention flop?
- Q193. What are the care about for retention flop secondary pin routing?
- Q194. What is the difference between a destination isolation cell and source isolation cell?
- Q195. When do we need level shifters?
- Q196. What's the effect on setup and hold if we reduce the frequency (increasing the clock period)?
- Q197. Does hold depends on frequency?
- Q198. What type of EM violations you addressed in your career?
- Q199. If I randomly pick one cell in my design, then what is the power that cell will have in static and in vector less IR drop analysis?
- Q200. What is tie-high and tie-low cells and where it is used?
- Q201. Why antenna violation come on signal net, but not on power net?
- Q202. How you will fix half cycle path?
- Q203. What are the technique to fix cross talk?
- Q204. How body biasing affects the timing?
- Q205. Can we get 0 skew what is the problem?
- Q206. On a post signoff DB, if we increase the frequency, what will happen?
- Q207. does the noise glitch always impact my device functionality?
- Q208. relationship between timing window and frequency of the design?
- Q209. if you want to improve the performance which one you change in ur design uncertainty or Frequency?
- Q210. how do you improve dynamic power in your design without considering architectural Changes?
- Q211. what is threshold voltage? How does it affect cell propagation delay?
- Q212. What is Power aware placement?
- Q213. HVT vs ULVT scaling across corners, which one would you prefer to fix hold if the path is also setup critical?
- Q214. How do you fix Dynamic voltage drop?
- Q215. What are the factors that affect Vt?
- Q216. What happens to Vt when Temp incr? why?
- Q217. What happens to mobility when Temp incr? Why?
- Q218. Does mobility keep decreasing with increasing in Temp?
- Q219. PMOS (holes) vs NMOS (electron) mobility?
- Q220. What does delay of a cell depend on?
- Q221. What happens to power and timing when clk transition is bad?
- Q222. What happens to setup and hold when clk transition is bad?
- Q223. Why mesh over regular CTS?
- Q224. Will you place your clock gates near the sink or the root?
- Q225. What is power gating?
- Q226. What is an isolation cell? How do you decide on using an AND gate or an OR gate to implement the isolation cell?
- Q227. Sources of Clock Skew at pre-CTS?
- Q228. What is Jitter and their sources?
- Q229. Difference between Clock buffer and regular buffer
- Q230. Miller Effect?
- Q231. Pre & post-route correlation.
- Q232. Post-route & Signoff timing correlation
- Q233. ICC Vs Extraction Correlation
- Q235. Why PMOS & NMOS in Transmission gate has always same area?
- Q236. Explain CEL and FRAM view ?
- Q237. what’s the reason behind tapping n-well to VDD & p-substrate to VSS?
- Q238. Well Edge Proximity (WEP) effect:
- Q239. Why Metal Density Rule needed?
- Q240. Explain ECO Extraction.
- Q241. STAR-RC & PT ECO Flow.
- Q242. Do we perform dynamic/static IR drop analysis for all modes (functional, scan capture, scan shift)?
- Q243. In how many corners we will do IR drop analysis?
- Q244. What is data toggle rate for static IR drop analysis/dynamic?
- Q245. Does any relationship between dynamic IR drop target to static IR drop target? (Dynamic IR drop target < = 3*Static IR drop target).
- Q246. what is ramp up voltage? How will it vary? how to calculate? how it impacts the IR drop analysis?
- Q247. off_state_leakage current? how will impact the IR drop?
- Q248. multi bit flip-flop designs pros & cons?
- Q249. Does jitter affect the hold violations? ·
- Q250. Does Jitter affect the setup violations?
- Q251. What are the recommended settings for designs with complex or fragmented floorplans?
- Q252. What will you look for netlist while floor planning?
- Q253. TCL proc for palindrome
- Q254. How to open a file and print line starting with error?
- Q255. Why do only cell delays have aocv and not wire delays? (wire delays are flat derates, no acov). How about wire delays? They depend on OPC etc right which is also random? (wire width variation based on OPC techniques like etching etc right. This etching process is not uniform across entire chip and that varies from one location to another depends on metal density in that area. That means as metal width is due to less etching and its width gets reduced if etching is excessive. wire delays will change from one place to other right? that means this is also random right?). Then why are we using flat derates?
- Q256. If you have an always on domain and a switching domain, where will you place the isolation cell?
- Q257. What ae the components of Power?
- Q258. How can you reduce Dynamic power?
- Q259. Where do you get the activity factor from?
- Q260. How you determine activity factor for input ports?
- Q261. If you are failing transition on a net routed over a macro. How do you fix transition with minimal rerouting?
- Q262. What is the short circuit current? How transition affects short circuit current
- Q263. what is AWP (advance wave propagation)
- Q264. In case, if you have access to only timing report at post route. What are the factors you will look into to improve setup timing?
- Q265. What are the design issues with higher Input transition?
- Q266. What is the difference between drive strength and fanout?
- Q267. What is the need of models in CMOS design?
- Q268. What are the inputs for .lib?
- Q269. What are the outputs of .lib?
- Q270. Why is input capacitance similar for higher drive?
- Q271. Why is LOOKUP table used for .libs?
- Q272. What is the information capture in LIB?
- Q273. What is the information capture in LEF?
- Q274. Why is thick metal layer need more spacing?
- Q275. What is the use of TLU-PLUS files?
- Q276. What is mapping file and where all it is required?
- Q277. How to create basic SDC for any new design?
- Q278. How to validate SDC?
- Q279. What happen if one AND gate is not having timing arc in lib and used in design?
- Q280. Create_generated_clock -invert/-combination
- Q281. Things needs to be reset in design
- Q282. Limitations on power via.
- Q283. Why is routing blockage defined at DIE edge?
- Q284. Why is TAP cells required?
- Q285. What is the type of physical only cells in design?
- Q286. Why is CORE to DIE spacing required in all sides?
- Q287. What is the factor limiting the macro orientation in design?
- Q288. Is Macro needs to aligned to STD rows?
- Q289. Can macro be placed at DIE boundary?
- Q290. Can there be macro in IO placement area in FULL chip?
- Q291. How to decide metal layer for power planning?
- Q292. Top down vs bottom -up:
- Q293. How to avoid Xtalk
- Q294. How to fix hold after routing?
- Q295. DRV vs setup, hold; which will have more priority
- Q296. What is what-if analysis in STA?
- Q297. What is the difference between “nworst 1” and “max_path 1” in report_timing command?
- Q298. Timing categorise:
- Q299. Steps to solve any setup and hold problems?
- Q300. Multi-Cycle Path HOLD and Setup violation fixing techniques.
- Q301. Steps to solve multi-cycle problems:
- Q302. Steps in fixing the setups timing:
- Q303. SPEF EXTRACTION
- Q304. Case_analysis
- Q305. What are the valid start points of any design?
- Q306. What are the valid endpoints?
- Q307. Why is derate applied only on capture clock path?
- Q308. Why is DFF used over JK flops?
- Q309. Useful Skew
- Q310. Hold fixing after tapeout?
- Q311. Can it be same launch – capture path be critical?
- Q312. What is the need of MV designs?
- Q313. Why is ISO required for ON-OFF design?
- Q314. What are the cells used in low power cells techniques?
- Q316. How do you know that you design is SW design by checking all design inputs?
- Q317. How to find the design needed power switch?
- Q318. What are the power saving techniques?
- Q319. Placement Targets:
- Q320. Placement Inputs
- Q321. Placement results
- Q322. Placement constraints
- Q323. Placement Checks.
- Q324. Design starting utilization and congestion analysis
- Q325. Placement Output:
- Q326. Placement Commands:
- Q327. What is need of early clock (estimation of clock in placement) flow in PD in lower technology?
- Q328. What is banking and de-banking in synth and how this will help in saving power?
- Q329. What are the power strap vios in design?
- Q330. Why is incremental optimization help in vios fixing?
- Q331. What is need of critical range?
- Q332. Difference between Hier and flat?
- Q333. Why is DECAP called local supply source?
- Q334. Disadvantage of clock gating
- Q335. Metal Layer allocation in design
- Q336. Pros and Cons of CTS scheme
- Q337. Pros and cons of NDR
- Q338. Why is mixing of VT types are not allowed in CTS?
- Q339. Max Transition analysis
- Q340. Why are metal layers taller in lower technology?
- Q341. CGC vios fixing techniques:
- Q342. Checks at CTS.
- Q343. CTS Inputs:
- Q344. CHECKS after CTS
- Q345. CTS Targets.
- Q346. How to decide on minimum insertion delay of block?
- Q347. What is the impact if insertion delay of the memory and macro not defined during CTS?
- Q348. Why is there a guideline for flops, keeping outside channels?
- Q349. Why is clock transition better than data transition?
- Q350. Why are clock nets have extra spacing?
- Q351. Factor in deciding the clock gating cell placement
- Q352. NDR, non-default routing rules.
- Q353. Why is XTALK so important in design?
- Q354. Why is spacing preferred over shielding of clock nets?
- Q355. Is shielding or spacing hard constraints or soft constraints for clock nets?
- Q356. Why is shielding percentage reduced at post_route stage compares to CTS stage?
- Q357. Select the cells required for CTS
- Q358. Debug steps for hold fixing:
- Q359. Fixing timing on clock gating vios:
- Q360. Command to report all vios to clock_gater
- Q361. Hold fixing:
- Q362. Macro Model:
- Q363. CTS Build STEPs
- Q364. CTS Checks:
- Q365. Clock_gating vios:
- Q366. Checks after routing
- Q367. Reporting in Routing
- Q368. What is Z in routing command?
- Q369. How to fix open and shorts?
- Q370. Design details to be capture for Floorplan, Place, CTS, Route, and final.
- Q371. Design techniques during ECO phase
- Q372. Buffer insertion
- Q373. Changing the metal layer for net
- Q374. What is interactive design mode of execution? Explain the need of this.
- Q375. FUNCTIONAL ECOS:
- Q376. Why is Dynamic IR drop in middle of chip where power stripe is connected?
- Q377. What is change in lower technology for DFM, single via?
- Q378. What is the problem seen with FILL metal?
- Q379. LATCHUP IN CMOS
- Q380. If foundry has 100% stable manufacturing, will you still choose DFM?
- Q381. Two metal shapes we have in the design and one metal shape with 1X width and
other metal shape of same layer with 2X width. What changes you can expect in delay of
these two metal shapes?
- Q382. Out if the following two dbs, which one would you pick and why?
1) with huge insertion delay and minimal skew.
2) with less insertion delay and more skew.
Timing of the block is better in case 1.
- Q383. What are the differences between 14nm and 7nm?
- Q384. All the violations in the design are clean, except one transition violation. Can we tapeout our design?
- Q385. In the picture attached, comment on possibility of antenna violation in each case, with reason.
(Given length of M3 alone as we are focusing on M3 antenna alone)
- Q.386. What is the difference between 'giving mcp of 2 for setup in between flopA to flopB and adding a register in between flopA and flopB?
If same, do we have any complications involved in implementing latter case?
- Q.387. Two clocks(clka and clkb) generated outside the block from same master clock, those two clocks entered your block through ports and you have clock definitions on ports in your block.
1) Will the PNR tool treat them as asynchronous clocks or synchronous clocks?
2) If you want tool to treat them as synchronous, what would be constraint?
- Q388. Why clock gating is timing critical in the design?
- Q.389. why do we have different thickness for different metal layers? And why is that the thickness of the metal layer increases from bottom layer towards top and not the other way round? Why it can't be constant for all the metal layers?
- Q.390. What do you mean by STA?
- Q.391. Why timing analysis is an important factor?
- Q.392. How many types of timing analysis are done in VLSI?
- Q.393. What are the important features of STA?
- Q.394. During timing analysis, what are the ideal characteristics of a clock?
- Q.395. What are the major functions of STA?
- Q.396. Which input files are required to run STA?
- Q.397. When Static Timing Analysis is done?
- Q.398. How STA is different from circuit simulation?
- Q.399. How STA is performed on the circuit?
- Q.400. For timing analysis, what are the various paths that the designer consider?
- Q.401. What do you mean by timing path? What are the start and endpoints?
- Q.402. In the synchronous circuit, what is the first stage of timing delay?
- Q.403. What are the various timing paths that a designer to go through?
- Q.404. What do you mean by launch edge and capture edge?
- Q.405. What do you mean by setup time and hold time?
- Q.406. Which factors decide setup time and hold time?
- Q.407. What do you mean by setup time and hold time violation?
- Q.408. What are the main reasons for setup or hold time violations?
- Q.409. What do you mean by critical path, false path, and multicycle path?
- Q.410. What is the worst path and best path?
- Q.411. Out of setup time violation and hold time violation, which is more dangerous to the design specifications and working mode?
- Q.412. What do you mean by the term “time borrowing”?
- Q.413. What do you understand by time stealing?
- Q.414. What are the main characteristics of the time borrowing concept?
- Q.415. What is the difference between time borrowing and timestealing?
- Q.416. How will you calculate negative borrow time and maximum borrow time?
- Q.417. What do you mean by positive, negative and zero slack?
- Q.418. How will you measure slack for setup and hold time?
- Q.419. Enlist the ideal conditions for the timing path?
- Q.420. What do you mean by clock skew? What is positive, negative and zero clock skew?
- Q.421. How does the clock skew violate setup and hold time constraints?
- Q.422. What do you mean by clock jitter?
- Q.423. How many types of clock jitter are there?
- Q.424. Which type of jitters can be used to determine highfrequency jitter?
- Q.425. What do you mean by reset? How many types of resets are available?
- Q.426. Explain the concept of synchronous reset along with its advantages and disadvantages?
- Q.427. Explain the concept of asynchronous reset along with its advantages and disadvantages?
- Q.428. What do you mean by reset assertion and reset Deassertion?
- Q.429. What is reset recovery time?
- Q.430. What do you mean by reset removal time?
- Q.431. Explain the concept of a lockup latch?
- Q.432. If the clock skew is large, can you use buffers to avoid hold time constraints violation?
- Q.433. What are the advantages of a lockup latch?
- Q.434. Is there any difference between the lockup latch and lockup register?
- Q.435. What do you understand by the term ‘clock latency’?
- Q.436. Is the term clock skew and global skew the same?
- Q.437. Can you fix the timing path? If yes, then give at least three ways to fix the timing path?
- Q.438. What is a false path in static timing analysis?
- Q.439. What is one hot encoding method?
- Q.440. What is the concept of a multicycle path?
- Q.441. How a multicycle path is achieved by the timing tool?
- Q.442. What do you mean by cell delay and net delay?
- Q.443. Enlist the parameters on which net delay or cell delay depends?
- Q.444. What is the worst delay and best delay?
- Q.445. Enlist types of delay models used to estimate the delay?
- Q.446. What is static sensitization?
- Q.447. What do you mean by signal integrity issues?
- Q.448. What do you mean by crosstalk?
- Q.449. How can you avoid crosstalk?
- Q.450. How the spacing reduces the crosstalk?
- Q.451. How multiple vias are used to reduce crosstalk?
- Q.452. What is the difference between crosstalk noise and crosstalk delay?
- Q.453. Elaborate on the concept of OCV (on-chip variation)?
- Q.454. Enlist any two sources of on-chip variation (OCV)?
- Q.455. What do you understand by the clock generator and clock distributor?
- Q.456. What are global chip-to-chip variation and local on-chipvariation?
- Q.457. What are the two main clock distribution styles in VLSI?
- Q.458. What is the clock grid distribution system?
- Q.459. Explain the concept of the clock mesh distribution system?
- Q.460. What is a clock tree distribution system?
- Q.461. What is the difference between the clock mesh and clock tree-type distribution system?
- Q.462. Are clock tree synthesis and clock tree distribution, the same thing?
- Q.463. What is the need for clock gating?
- Q.464. What is the significance of CRPR in static timing analysis?
- Q.465. What is DEF and what is its use?
- Q.466. Explain the term metastability?
- Q.467. What are the effects of metastability?
- Q.468. What are the reasons for metastability?
- Q.469. How metastability can be avoided or tolerated in a circuit?
- Q.470. Can you synchronize between two clock domains?
- Q.471. What is the role of synchronizer?
- Q.472. How latch and flip-flops are related?
- Q.473. The device delay is dependent on which factors?
- Q.474. What is the difference between statistical and conventional STA?
- Q.475. Enlist the major tools that are available for STA?
- Q.476. What are all the items that are checked by static timing analysis ??
- Q.477. If hold violation exists in design, is it OK to sign off design? If not, why?
- Q.478. What are setup and hold checks for clock gating and why are they needed ?
- Q.479. What determines the max frequency a digital design will work on. Why hold time is not included in the calculation for the above ?
- Q.480. One chip which came back after being manufactured fails setup test and another one fails a hold test. Which one may still be used how and why ?
- Q.481. Explain clock jitter and its sources?
- Q.482. What are the advantages of NDR's?
- Q.483. what is the concept of rows in the floorplan?
- Q.484. What is temperature inversion?
- Q.485. How can you reduce dynamic power?
- Q.486. Why double via insertion
- Q.487. what is metal fill insertion?
- Q.488. what is metal slotting ?
- Q.489. what is dishing effect ?
- Q.490. what are the violations solved in LVS?
- Q.491. What is Wire load model (wlm)
- Q.492. How a positive or negative edge triggered flip flop will effect the setup and hold violations ?
- Q.493. if we increase the fanout of the cell how it will effect delay?
- Q.494. What is multidriven nets?
- Q.495. what is magnet placement?
- Q.496. what are the checks done in primetime?
- Q.497. for creating proper MMMC view definitions what information is required ?
- Q.498. Difference between DRV and DRCs ?
- Q.499. What is the role of ERC ?
- Q.500. what happens if assign statements are not present in synthesized netlist ?
