Physical Design MCQs

1. Chip utilization depends on ___.

a. Only on standard cells b. Standard cells and macros c. Only on macros d. Standard cells macros and IO pads

2. In Soft blockages ____ cells are placed.

a. Only sequential cells b. No cells c. Only Buffers and Inverters d. Any cells

3. Why we have to remove scan chains before placement?

a. Because scan chains are group of flip flop b. It does not have timing critical path c. It is series of flip flop connected in FIFO d. None

4. Delay between shortest path and longest path in the clock is called ____.

a. Useful skew b. Local skew c. Global skew d. Slack

5. Cross talk can be avoided by ___.

a. Decreasing the spacing between the metal layers b. Shielding the nets c. Using lower metal layers d. Using long nets

6. Prerouting means routing of _____.

a. Clock nets b. Signal nets c. IO nets d. PG nets

7. Which of the following metal layer has Maximum resistance?

a. Metal 1 b. Metal 2 c. Metal 7 d. Metal 5

8. What is the goal of CTS?

a. Minimum IR Drop b. Minimum EM c. Minimum Skew d. Minimum Slack

9. Usually Hold is fixed ___.

a. Before Placement b. After Placement c. Before CTS d. After CTS

10. To achieve better timing ____ cells are placed in the critical path.

a. HVT b. LVT c. RVT d. SVT

11. Leakage power is inversely proportional to ___.

a. Frequency b. Load Capacitance c. Supply voltage d. Threshold Voltage

12. Filler cells are added ___.

a. Before Placement of std cells b. After Placement of Std Cells c. Before Floor planning d. Before Detail Routing

13. Search and Repair is used for ___.

a. Reducing IR Drop b. Reducing DRC c. Reducing EM violations d. None

14. Maximum current density of a metal is available in ___.

a. .lib b. .v c. .tf d. .sdc

15. More IR drop is due to ___.

a. Increase in metal width b. Increase in metal length c. Decrease in metal length d. Lot of metal layers

16. The minimum height and width a cell can occupy in the design is called as ___.

a. Unit Tile cell b. Multi height cell c. LVT cell d. HVT cell

17. CRPR stands for ___.

a. Cell Reconvergence Pessimism Removal b. Cell Reconvergence Preset Removal c. Clock Reconvergence Pessimism Removal d. Clock Convergence Preset Removal

18. In OCV timing check, for setup time, ___.

a. Max delay is used for launch path and Min delay for capture path b. Min delay is used for launch path and Max delay for capture path c. Both Max delay is used for launch and Capture path d. Both Min delay is used for both Capture and Launch paths

19. Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.

a. Utilization b. Aspect Ratio c. OCV d. Antenna Ratio

20. The Solution for Antenna effect is ___.

a. Diode insertion b. Shielding c. Buffer insertion d. Double spacing

21. To avoid cross talk, the shielded net is usually connected to ___.

a. VDD b. VSS c. Both VDD & VSS d. Clock

22. If the data is faster than the clock in Reg to Reg path ___ violation may come.

a. Setup b. Hold c. Both d. None

23. Hold violations are preferred to fix ___.

a. Before placement b. After placement c. Before CTS d. After CTS

24. Which of the following is not present in SDC ___?

a. Max tran b. Max cap c. Max fanout d. Max current density

25. Timing sanity check means (with respect to PD)___.

a. Checking timing of routed design with out net delays b. Checking Timing of placed design with net delays c. Checking Timing of unplaced design without net delays d. Checking Timing of routed design with net delays

26. Which of the following is having highest priority at final stage (post routed) of the design ___?

a. Setup violation b. Hold violation c. Skew d. None

27. Which of the following is best suited for CTS?

a. CLKBUF b. BUF c. INV d. CLKINV

28. Max voltage drop will be there at(with out macros) ___.

a. Left and Right sides b. Bottom and Top sides c. Middle d. None

29. Which of the following is preferred while placing macros ___?

a. Macros placed center of the die b. Macros placed left and right side of die c. Macros placed bottom and top sides of die d. Macros placed based on connectivity of the I/O

30. Routing congestion can be avoided by ___.

a. placing cells closer b. Placing cells at corners c. Distributing cells d. None

31. Pitch of the wire is ___.

a. Min width b. Min spacing c. Min width - min spacing d. Min width + min spacing

32. In Physical Design following step is not there ___.

a. Floorplaning b. Placement c. Design Synthesis d. CTS

33. In technology file if 7 metals are there then which metals you will use for power?

a. Metal1 and metal2 b. Metal3 and metal4 c. Metal5 and metal6 d. Metal6 and metal7

34. If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

a. Metal1 and metal2 b. Metal3 and metal4 c. Metal4 and metal5 d. Metal6 and metal7

35. In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

a. 1ns b. 3ns c. 5ns d. 6ns

36. Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/inverters b. Clock buff/inverters are slower than normal buff/inverters c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.

37. Which configuration is more preferred during floorplaning ?

a. Double back with flipped rows b. Double back with non flipped rows c. With channel spacing between rows and no double back d. With channel spacing between rows and double back

38. What is the effect of high drive strength buffer when added in long net ?

a. Delay on the net increases b. Capacitance on the net increases c. Delay on the net decreases d. Resistance on the net increases.

39. Delay of a cell depends on which factors ?

a. Output transition and input load b. Input transition and Output load c. Input transition and Output transition d. Input load and Output Load.

40. After the final routing the violations in the design ___.

a. There can be no setup, no hold violations b. There can be only setup violation but no hold c. There can be only hold violation not Setup violation d. There can be both violations.

41. Utilisation of the chip after placement optimisation will be ___.

a. Constant b. Decrease c. Increase d. None of the above

42. What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracks b. Ratio of available routing tracks to required routing tracks c. Depends on the routing layers available d. None of the above

43. What are preroutes in your design?

a. Power routing b. Signal routing c. Power and Signal routing d. None of the above.

44. Clock tree doesn't contain following cell ___.

a. Clock buffer b. Clock Inverter c. AOI cell d. None of the above

45. Power Switch off (PSO) | Power Gating technique in low power is used to reduce

a. Dynamic Power b. Leakage Power c. Internal Power d. A & B

46. Why do we re-order scan chains during placement?

a. Because scan chains are group of flipflop b. it does not have timing critical path c. Existing scan is not physically aware d. None

47. Increase in the physical distance of H-tree _________the skew rate.

a. Increases b. Stabilizes c. Decreases d. All of the above

48. In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?

a. Floorplanning b. Placement & Routing c. Testing d. Extraction

49. clock buffers are preferred than normal buffers in clock tree building because of

a. 50% duty cycle b. better power c. better area d. lesser transition

50. Select based on their priority

a. Area > Timing > Power b. Timing > Power > Area c. Power > Timing > Area d. Timing > Area > Power

51. Timing Arc can be from an output to an input, as in bidirectional ports.

a. True b. False c. Maybe

52. How many positive unate arcs does the two input NOR gate have ?

a. 4 b. 1 c. 2 d. 0

53. How many arcs does the two input OR gate have ?

a. 4 b. 1 c. 2 d. 0

54. Static timing analysis is used mainly in ?

a. Logic Optimization b. Timing Verification c. Logic opt. and timing verification d. Functional Verification and Logic Verification e. All of the above

55. What do the STA tools use to determine the wire-load model ?

a. Length of the net b. Block Area c. Resistance and Capacitance d. None of the above

56. Interconnects ARCS are ?

a. Negatively Unate b. Positively Unate c. NonUnate d. None of the above

57. Clock latency includes __ : select all that apply.

a. External Latency b. Internal Latency c. clock delay from clock source to the clock pin, or source latency d. Delay due to the clock buffer, or clock tree delay, or network latency.

58. You can remedy Setup time violation by ?

a. Speeding up the data or increase the clock period b. Speeding up the data and the clock c. Increasing the data delay to the flop d. Increasing the clock speed

59. You can remedy Hold time violation by ?

a. Reducing clock skew or uncertainty b. Increasing the data delay to the flop c. Increasing the clock speed and speed up the data

60. When constraining designs in ideal mode, clock uncertainty is usually set to the value of ?

a. Clock skew b. Clock slewp c. Clock jitter + clock skew d. Clock jitter + clock slew

61. When constraining designs in Propagated mode, clock uncertainty is usually set to the value of ?

a. Clock Jitter b. Clock slewp c. Clock jitter + clock skew d. Clock jitter + clock slew

62. Which of the following used for N-Well Continuity ?

a. End-Cap Cell b. De-Cap c. Filler Cell d. Both A & C

63. In a DataPath with Crosstalk, if aggressor and victim have same transition direction. It aids in ?

a. Setup b. Hold c. Does not affect d. Affects both setup and hold

64. Which Statemnt is True ?

a. LVT Cell have more leakage than SVT b. SVT has more leakage then LVT c. HVT has less delay then SVT d. All are incorrect

65. LVS consists of following steps ?

a. Extraction, Comparison b. Extraction, Reduction, Comparison c. Reduction, Comparison d. Comparison

66. Solution for antenna affect is ?

a. Diode Insertion b. Shielding c. Buffer Insertion d. Double Spacing

66. ERC Stands for ?

a. Electromigration Check b. Electrical Rule Check c. Engineering Rule check d. None of the above

67. Spare cell are comprised for ?

a. only combinational logic b. Only Universal gates NAND & NOR c. Combinational Macro and IO d. All of the above

68. What are the components of uncertainty before CTS ?

a. Skew + Margin b. Jitter + Skew c. Jitter + Margin d. Skew + Jitter + Margin

69. What to do if pin density is more for specific hierarchy ?

a. Partial blockages b. Use bounds c. Magnet Placement d. Keepout margin

70. What to do if pin density is more for specific hierarchy ?

a. Partial blockages b. Use bounds c. Magnet Placement d. Keepout margin

71. What to do if cell density is more for specific hierarchy ?

a. Partial blockages b. Path grouping c. Magnet Placement d. Keepout margin

72. Routing Congestion can be avoided by ?

a. Placing cells closer b. Placing cells at corners c. Distributing cells d. None of the above

Importance of Routing as Technology Shrinks
Routing Objectives
Routing
Routing Inputs
Routing Goals
Routing constraints
Routing Flow
Trial/Global Routing
Track Assignment
Detail/Nano Routing
Grid based Routing
Routing Preferences
Post Routing Optimization
Filler Cell Insertion
Metal Fill
Spare Cells Tie-up/ Tie-down

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IO Pads
Types of IO Pads

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Delay Models

Delay Calculation
Delay Models
Interconnect Delay Models
Cell Delay Models

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ECO

Engineering Change Order
Post Synthesis ECO
Post Route ECO
Post Silicon ECO
Metal Layer ECO Example

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Types of Std cells

std cell library types
Classification wrt density and Vth

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DFM/DFY

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MC/MM/OCV

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