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  • IO Pads
    •  -Input Output Pads
    -Structure of Pad
    -Implementation Guidelines
    -Pad Limited Design
    -Core Limited Design
  • Types of IO Pads
    •  -Staggered IO Pads
    -Flip Chip IO Bumps
















    IO Design

    IO Design

    IO Pads

    Input Output Pads
    • Input/ Output circuits (I/O Pads) are intermediate structures connecting internal signals from the core of the integrated circuit to the external pins of the chip package
    • Typically I/O pads are organized into a rectangular Pad Frame
    • The input/output pads are spaced with a Pad Pitch
    • Pads will have pins on all metal layers used in design for easy access while routing the design
    • Number of layers depends on technology
    • Multiple Power Pads are often used to reduce the power
    • Pads consists of some logic cells like level shifters and buffers which will control the voltages of input and output signals and to increase/ decrease drive strength physical design input output ports
    Structure of Pads
    • Bonding Pad
      • Area to which the bond wire is soldered
      • The wire goes from the bonding pad to a chip pin
    • ESD (Electrostatic Discharge) protection circuitry consisting of a pair of big PMOS, NMOS in a reverse biased diode structure
    • Driving and Logic Circuitry for which the area of is designated pad in physical design

    Implementation Guidelines
    • Isolate sensitive asynchronous inputs such as Clock or Bidirectional Pins from other switching pads with Power/Ground Pads
    • Group Bidirectional Pads together such that all are in the input/ output mode
    • Avoid continuous placing of simultaneous switching pads
    • 2 extra pins = 1 extra pad on 2 sides and 4 extra pins = 1 extra pad on each side
    • Power supply pads must be evenly distributed
    • The number of Power Pads required are calculated based on the IO Signal Pads power requirement and Core Power requirement (IR drop limit)
    • No. of IO Power Pads required in a design, Thumb Rule: One Pair of Power Pads for every 4 or 6 Signal Pads
    • No. of Core Power Pads required in a design, IO Signals in physical design
    Pad Limited design
    • The area of Pad limits the size of Die
    • No. of IO pads are more or larger in size (technology dependent)
    • Pad limited designs pose several challenges for design implementation and to the backend designers, if Die area is a constraint
    • The Solution would be to use Flip Chip or Staggered IO placement techniques
    Core Limited Design
    • The area of Core limits the size of Die
    • No. of IO Pads are lesser
    • In these designs Inline IOs will be used
    • It can be either due to large no. of Macros the design or due to larger logic
    core limited design pad limited design



    Types of IO Pads

    Types of Pads according to Logic directions
    • Input Pad
    • Output Pad
    • Bidirectional Pad
    IO Pads

    Types of Pads according to Logic Styles
    • Signal Pads
    • Power Pads (Core Power and IO Power)
    • Corner Pads
      • Corner pads contains only connections in all metal layers defined in technology
      • These pad used only for IO Ring continuity and chip metal density on corners and to maintain yield
    • Filler Pads
      • IO Filler Cells contains only the geometrical information of the Power Rings in all metal layers
      • Continuity of Power Rings which is responsible for uniform distribution of power
      • Electrostatic Discharge protection
    According to the Pad locations
    • Peripheral IO Pads
    • Area IO Pads
      IO Pad location
    Types of Pads according to Implementation Styles
    • Inline
    • Staggered
      • CUP (Circuit-Under-Pad)
      • Non-CUP (Circuit-Under-Pad)
    • Flip Chip
    Inline IO Pads
    Inline IO Pad
    • Pads are placed next to each other, with the corresponding bond pads lined up against each other having a small gap in between
    • Minimum Pitch is determined by foundry/vendor and is technology dependent
    Staggered IO Pads
    CUP (Circuit-Under-Pad)
      staggered IO pads
    • Bonding Pad over the IO body itself
    • Bonding Pad have to connected to the PAD Pin of IO
    • Pad pin is located close to the center of the IO body for easier routing, signal integrity, and space saving
    • Reduce the die size since the Bonding Pad does not take any extra space in addition to the IO body itself
    • Advantages include more no. of IO’s, Optimal area utilization, Lower cost
    Non-CUP (Circuit-Under-Pad)
      circuit under pad
    • Useful technique if design is “Pad Limited”
    • Place an inner and outer Bond Pad alternately
    • A larger number of pads can be accommodated
    • Disadvantage is that the overall height of the pad structure increases significantly
    Flip Chip IO Bumps
    • It is simply a direct connection of a flipped electrical component onto a substrate, carrier, or circuit board by means of conductive Bumps instead of the conventional Wire-bond
    • In Flip Chip, IO Bumps and driver cells may be placed in the peripheral or core area
    • Note, the large octagonal area IO Bumps overlaying placed cells in the core area
    • No chip area benefit for small chips – full Bump array redistribution is very difficult
    • In advanced technology nodes a separate Re-distribution layer (RDL) is make use of for the Bump connections flip chip

    • What is synthesis?
    • Goals of synthesis
    • Synthesis Flow
    • Synthesis (input & output)
    • HDL file gen. & lib setup
    • Reading files
    • Design envi. Constraints
    • Compile
    • Generate Reports
    • Write files
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    • Netlist(.v or .vhd)
    • Constraints
    • Liberty Timing File(.lib or .db)
    • Library Exchange Format(LEF)
    • Technology Related files
    • TLU+ File
    • Milkyway Library
    • Power Specification File
    • Optimization Directives
    • Design Exchange Formats
    • Clock Tree Constraints/ Specification
    • IO Information File
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    • import design
    • sanity checks
    • partitioning (flat and hierarchy)
    • objectives of floorplan
    • Inputs of floorplan
    • Floorplan flowchart
    • Floorplan Techniques
    • Terminologies and definitions
    • Steps in FloorPlan
    • Utilization
    • IO Placement
    • Macro Placement
    • Macro Placement Tips
    • Blockages (soft,hard,partial)
    • Halo/keepout margin
    • Issues arises due to bad floor-plan)
    • FloorPlan Qualifications
    • FloorPlan Output
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    • levels of power distribution
    • Power Management
    • Powerplanning involves
    • Inputs of powerplan
    • Properties of ideal powerplan
    • Power Information
    • PowerPlan calculations
    • Sub-Block configuration
    • fullchip configuration
    • UPF Content
    • Isolation Cell
    • Level Shifters
    • Retention Registers
    • Power Switches
    • Types of Power dissipation
    • IR Drop
    • Electromigration
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    • Pre-Placement
    • Pre-Placement Optimization
    • Placement
    • Placement Objectives
    • Goals of Placement
    • Inputs of Placement
    • Checks Before placement
    • Placement Methods(Timing & Congestion)
    • Placement Steps
    • Placement Optimization
    • Placement Qualifications
    • Placement Outputs
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    • Pre-CTS Optimization
    • CTS
    • Diff b/w HFNS & CTS
    • Diff b/w Clock & normal buffer
    • CTS inputs
    • CTS Goals
    • Clock latency
    • Clock problems
    • Main concerns for Clock design
    • Clock Skew
    • Clock Jitter
    • CTS Pre requisites
    • CTS Objects
    • CTS Flow
    • Clock Tree Reference
    • Clock Tree Exceptions
    • CTS Algorithm
    • Analyze the Clock tree
    • Post CTS Optimization
    • CTS Outputs
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    • Importance of Routing as Technology Shrinks
    • Routing Objectives
    • Routing
    • Routing Inputs
    • Routing Goals
    • Routing constraints
    • Routing Flow
    • Trial/Global Routing
    • Track Assignment
    • Detail/Nano Routing
    • Grid based Routing
    • Routing Preferences
    • Post Routing Optimization
    • Filler Cell Insertion
    • Metal Fill
    • Spare Cells Tie-up/ Tie-down
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    • Diff b/w DTA & STA
    • Static Timing Analysis
    • main steps in STA
    • STA(input & output)
    • Timing Report
    • Clocked storage elements
    • Delays
    • Pins related to clock
    • Timing Arc
    • Timing Unate
    • Clock definitions in STA
    • Timing Paths
    • Timing Path Groups
    • Clock Latency
    • Insertion Delay
    • Clock Uncertainty
    • Clock Skew
    • Clock Jitter
    • Glitch
    • Pulse width
    • Duty Cycle
    • Transition/Slew
    • Asynchronous Path
    • Critical Path
    • Shortest Path
    • Clock Gating Path
    • Launch path
    • Arrival Path
    • Required Time
    • Common Path Pessimism(CPP/CRPR)
    • Slack
    • Setup and Hold time
    • Setup & hold time violations
    • Recovery Time
    • Removal Time
    • Recovery & Removal time violations
    • Single Cycle path
    • Multi Cycle Path
    • Half Cycle Path
    • False Path
    • Clock Domain Crossing(CDC)
    • Clock Domain Synchronization Scheme
    • Bottleneck Analysis
    • Multi-VT Cells(HVT LVT SVT)
    • Time Borrowing/Stealing
    • Types of STA (PBA GBA)
    • Diff b/w PBA & GBA
    • Block based STA & Path based STA
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    • Congestion Analysis
    • Routing Congestion Analysis
    • Placement Cong. Analysis
    • Routing Congestion causes
    • Congestion Fixes
    • Global & local cong.
    • Congestion Profiles
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    • Power Analysis
    • Leakeage Power
    • Switching Power
    • Short Circuit
    • Leakage/static Power
    • Static power Dissipation
    • Types of Static Leakage
    • Static Power Reduction Techniques
    • Dynamic/Switching Power
    • Dynamic Power calculation depends on
    • Types of Dynamic Power
    • Dynamic Power Reduction Techniques
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    • IR Drop Analysis
    • Types of IR Drop & their methodologies
    • IR Drop Reasons
    • IR Drop Robustness Checks
    • IR Drop Impacts
    • IR Drop Remedies
    • Ldi/dt Effects
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    • Design Parasitics
    • Latch-Up
    • Electrostatic Discharge(ESD)
    • Electromigration
    • Antenna Effect
    • Crosstalk
    • Soft Errors
    • Sef Heating
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    • Cells in PD
    • Standard Cells
    • ICG Cells
    • Well Taps
    • End Caps
    • Filler Cells
    • Decap Cells
    • ESD Clamp
    • Spare Cells
    • Tie Cells
    • Delay Cells
    • Metrology Cells
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    • IO Pads
    • Types of IO Pads
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    • Delay Calculation
    • Delay Models
    • Interconnect Delay Models
    • Cell Delay Models
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    • Engineering Change Order
    • Post Synthesis ECO
    • Post Route ECO
    • Post Silicon ECO
    • Metal Layer ECO Example
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    • std cell library types
    • Classification wrt density and Vth
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    • The Discontinuity
    • Discontinuity: Classification
    • DFM/DFY
    • Yield Classification
    • Why DFM/DFY?
    • DFM/DFY Solution
    • Wire Spreading
    • metal Fill
    • CAA
    • CMP Aware-Design
    • Redundant Via
    • RET
    • Litho Process Check(LPC)
    • Layout Dependent Effects
    • Resolution Enhancement Techniques
    • Types of RET
    • Optical Proximity Correction(OPC)
    • Scattering Bars
    • Multiple Patterning
    • Phase-shift Masking
    • Off-Axis Illumination
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    • Corners
    • Need for corner analysis
    • PVT Variations
    • Corner Analysis
    • PVT/RC Corners
    • Temperature Inversion
    • Cross Corner Analysis
    • Modes of Analysis
    • MC/MM Analysis
    • OCV
    • Derating
    • OCV Timing Checks
    • OCV Enhancements
    • AOCV
    • SSTA
    • CRPR/CPPR
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