Answer:

1. Bit: Binary digit (Either logic-1 or logic-0)
2. Nibble: 4-bits together is called a nibble
3. Byte: 8 bits or 2 nibbles
4. Word: 16 bits or 2 bytes

Answer:
The weighted code will have a fixed weight for each position. For example, in normal binary system, the decimal equivalent can be obtained by multiplying the position value with position weight and adding them together.

Answer:
Unlike weighted code, non-weighted codes will not any weights. For example, Excess-3 code and Gray code. So the numbers that are represented using non-weighted code can not be directly converted to decimal equivalents.

Answer:
Self-complementing: The 9’s complement of an excess 3 number can be obtained simply by replacing its 1’s with 0’s and 0’s with 1’s.

Answer:
2-4-2-1 represents the weights corresponding to bit positions.
So the two possible ways are: 1011, 0101

Answer:
0, 1, 8 and 9 (Only these 4 numbers will have unique representations).

Answer:
As BCD numbers range from 0 to 9, there are 5 unused combinations in 7-4-2-1 code.
They are: 1011, 1100, 1101, 1110 and 1111.

Answer:
A weighted code is self-complimentary if the sum of the weights equals to 9.
E.g.: 2-4-2-1 code. Sum of the weights = 2+4+2+1 = 9

Answer:
(a) Binary: 011 101 010 001
     Octal:  3   5   2   1
(b) Binary: 0111 0101 0001
       Hex:   7   5   1

Answer:
Consider (X_n-1 X_n-2 ……..X₃ X₂ X₁ X₀) a n bit base 3 number.
The corresponding decimal equivalent is given by,
3^n-1 X_n-1 + 3^n-2 X_n-2 ….. + 3³ X₃ + 3²X₂ + 3¹X₁ + 3⁰X₀
= 9^(n-2)/2 (3 X_n-1 + X_n-2) + .............+ 9¹(3 X₃ + X₂) + 9⁰(3X₁ + X₀)
So take every to digits of base-3 number from LSB side, find their decimal equivalent, it will be the corresponding base-9 digit. (Similar to the procedure of converting a binary number to octal or hex)

Answer:
Base-3:(2 11 10 12 22 21 11 22)₃
Base-9: 2  4  3  5  8  7  4  8

Answer:
(rⁿ – 1)-N , (rⁿ – N)

Answer:
999 – 752 = 247

Answer:
Conversion from gray to binary: Retain the MSB as it as. XOR the current input bit with the previous output bit to get the new output bit. In this case, given gray code number is 11001


So, the required binary number is 10001.

Answer:
Binary to Gray code conversion: Retain MSB. XOR Current bit of Binary input with the previous bit of Binary input to get new bit of Gray code Output.

Answer:
(a) 101101
(b) To get BCD: Represent each digit separately in binary 0100 0101
(c) Excess-3: Add 3 to each digit and then represent them separately in binary 0111 1000
(d) Gray code: First convert to Binary and use the procedure shown in Q15: 111011

Answer:
–(2 ^{n – 1}) to +(2 ^{n – 1} – 1)

Answer:
(2 ^{n – 1} – 1) > 23 => 2 ^{n – 1} > 24 => 2 ^{n – 1} = 32 => n-1 = 5 => n = 6 bits

Answer:
2’s compliment of the binary number
E.g.: Consider 10010, Its 2’s compliment is given by 01110

Answer:
78B in hex = 01111.0111000 (5 integral bits and 7 fractional bits)
           = 15.4375

Answer:
0.95 x 2 = 1.90 ---- 1
0.90 x 2 = 1.80 ---- 1
0.80 x 2 = 1.60 ---- 1
0.60 x 2 = 1.20 ---- 1
0.20 x 2 = 0.40 ---- 0
0.40 x 2 = 0.80 ---- 0
0.80 x 2 = 1.60 ---- 1 ……….
So, 0.95 = 0. 11 1100 1100 1100 1100....

Answer:
AB₁₆ – 3E₁₆ = (171) – (62)
            = (109) = 6D₁₆

Answer:
) 2x²+ x + 1 = 56 + 50 = 106 => x (2x+1) = 105 = 7 x 15 => x = 7

Answer:
(78)₉ = 63 + 8 = (71)₁₀
(135)₁₂ = 144 + 36 + 5 = (181)₁₀
(71)₁₀ - (181)₁₀ = (110)₁₀ = (156)₈
So, X = 156

Answer:
BCD addition is similar to any binary addition. But if the result is above 9, to get valid BCD result, we need to add 6 to the result.

Answer:
  1 0 0 1
  0 1 1 0
----------------
 1 1 1 1 (>9)
6,0 1 1 0
----------------
  1 0 1 0 1
So, the result is 0001 0101 = (1 5)

Answer:
NAND and NOR gates are called universal gates. Because any other logical gate like AND, OR, NOT, XOR, XNOR etc. or any other Boolean function can be implemented only with NAND or NOR gates.

Answer:
For n inputs, possible minterms/maxterms = 2ⁿ. For example, for 2 inputs the possible 4 minterms are A’B’, A’B, AB’, AB and maxterms are A+B, A’+B, A+B’, A’+B’.

Answer:
(a) 6 = (0110)₂ Minterm = A’BCD’, maxterm = A+B’+C’+D (b) 15 = (1111))₂ Minterm = ABCD, maxterm = A’+B’+C’+D’

Answer:
A NAND gate can be converted into an inverter by using any of the following two methods:

Answer:
N-1. For example to implement a 4 input AND gate we need three 2-input AND gates.

Answer:
(A+B+C+D…)’ = A’.B’.C’.D’…….
(ABCD……..)’ = A’ + B’ + C’ + D’……

Answer:
(a) OR Gate.
We can conclude this from truth table. Also from Boolean algebra as shown here :
As A=B=1, can not occur, AB = 0 always.
A XOR B = AB’ + A’B = A (AB)’ + B (AB)’ = A (0)’ + B(0)’ = A + B

(b) XNOR Gate.
A XOR B = AB’ + A’B
Using this, A’ XOR B = AXOR B’ = A’B’ + AB = A XNOR B

Answer:
According to Shannon’s expansion theorem any Boolean function F(A,B,C,D….) can be represented as F = A F_A + A’ F_A’ , where the cofactors FA and FA’ are given as, F_A = F(1,B,C,D….) and F_A’ = F(0,B,C,D….)

Answer:
F_A = BD + BCD’ and F_A’ = BCD’ + B’C’

Answer:
F_A = BD + BCD’ and F_A’ = BCD’ + B’C’

Answer:
2^2^n For n inputs, the possible number of minterms are, k = 2^n.
Any boolean function is combination of minterms. So all possible Boolean functions are
^kC₀ + ^kC₁ + ^kC₂ + ^kC₃ + ……. ^kC_k = (1 + 1)^k = 2^k = 2^2^n

Answer:
First XOR gate output = X XOR X’ = 1
Second XOR output = 1 XOR X = X’
Third XOR gate output = OUT = X’ XOR X = 1
OUT = 1 irrespective of X

Answer:
A XOR B = A’B + AB’ = A(AB)’ + B(AB)’

Answer:
6
A = Switch B=Sensor1 C=Sensor2 D=Sensor3 Pressed or sensor activated = 1
F=Shutdown=1
If you use K-Map and simplify, you will get F = A + BC + CD. The implementation of the same is shown below.

Answer:
Truth table for 3-input majority function is shown below:

Answer:
This is circuit will work in two different ways based on N-value. (a) N is odd (b) N is even

(a) If N is odd, there will be even number of XNOR gates in the circuit. Take an example of N=3, So there are 2 XNOR Gates. The two bubbles will get cancelled and this works as XOR. Same works for any odd N. So if N is odd it works as XOR Gate.
(b) If N is even, the circuit works as XNOR Gate. ( Apply the same logic). One extra bubble will be there to make XOR to XNOR. You may verify the same for N=4.

Answer:
Very much similar to Answer 13.

Answer:
Parity generation adds an extra bit to the data which indicates the parity of input data. Parity generation is of two types: Even-parity and odd-parity generation. Even parity generator gives 1 if the input has odd number of 1’s so that overall number of 1’s will be even. Similarly odd parity generator gives 1 if the input has even number of 1’s.

In data transmission systems the transmission channel itself is a source of data error. Hence the need to determine the validity of transmitted and received data. The validity of data is essential in applications where data is transmitted over long distances. Invalid data is a corruption risk. Parity generation helps in checking the validity of the data. Parity generation and validation is a scheme to provide single bit error detection capabilities.

Answer:
XOR gate can be used as even parity generator and XNOR can be used as odd parity generator.

Answer:
(i) ODD as the number of ones = 5, odd number
(ii) EVEN, number of 1s =4,even

Answer:
The following circuit shows a parity checker for 4 inputs. A, B and C is the actual data. Whereas P is even parity bit generated at the transmitter. P = A xor B xor C. So A, B, C and P together will have even parity always. If all the bit sequences are received properly, O should be zero always. O=1 indicates that some error has occurred during transmission.

The same circuit can be used for parity generation by putting P = 0. If P=0, the same circuit works as 3-input even parity generator.

Answer:
The detailed procedure with an example for converting gray code to binary is shown in chapter 1. The same concept is shown with the XOR gates here.

Answer:
The input clock, the OUT that is needed and the corresponding CLK_EN are shown in the following diagram:

Answer:
XNOR gate.
If we observe the truth tables, XNOR gate gives 1 if both the inputs are same.
Similarly XOR gives 1 if both the signals are different.

Answer:

Answer:
Dual : Replacing AND (NAND) with OR(NOR) and OR (NOR) with AND(NAND) in a given boolean equation gives the dual.

Answer:
a) iv
b) iii
c) ii
d) i

Answer:
SOP: Sum Of Products : OR of all ANDs Eg: F (A,B,C) = A + BC
POS: Product Of sums: AND of all ORs Eg: F(A,B,C) = (A’+B’) (A’+C’)

Answer:
A SOP is called standard if each term is a minterm. Similarly a POS is called standard if each term is a maxterm.

Answer:

Answer:
(a) SOP form
(b) POS form

Answer:
Hamming order (Gray code)

Answer:
In K-Map, the Boolean simplification is done by grouping the adjacent cells that have 1. To get the simplified expression, the adjacent cells must have 1 bit change. So gray code is used.

Answer:
2ⁿ. E.g.: 3 variables, 8 cells. Similarly..4 variables 16 cells.

Answer:
Ceiling (log2 n)

Answer:
The don’t care condition set accommodates input patterns that never occur or outputs that will not be observed.

Answer:
Y = A'C + AC'B' and the output will be don’t care for A = C = 1. So the K-map will be as follows:

Thus the simplified expression for Y is AB’ + C

Answer:

Answer:
Y = П (2,3,6,8,10,11,13,14,15)

Answer:
8 terms, F = B’E (A + A’) (C+C’) (D+D’)

Answer:
6 – log₂4 = 6-2 = 4

Answer:
In 3 variable map, grouping all 8 cells will give zero literals in the term as it is logical 1 always. Similarly, in 4 variable map the same grouping will give 1 literals, in 5 a variable map it is 2 and so on..
So the literals in the term = N – log₂k

Answer:
Q-M Method

Answer:
Checkout for the columns which has only one entry (X), that term must be included in the simplified expression. So, that term will be essential.
(a) So the essential prime implicants are: BC and B’C’
(b) The simplified expression F = BC + B’C’ + CD’ = BC + B’C’ + B’D’

Answer:
Checkout for the columns which has only one entry (X), that term must be included in the simplified expression. So, that term will be essential.
(a) So the essential prime implicants are: BC and B’C’
(b) The simplified expression F = BC + B’C’ + CD’ = BC + B’C’ + B’D’

Answer:

Answer:
To simplify the Boolean function in POS form we need to map for 0s and them take the compliment of that function to get Y in POS form.

Answer:
As the input is a BCD number, the output will be don’t care for the input combinations, 10,11,12,13,14 and 15. So the K-Map will be as shown below:

Answer:
(a) For a 2:1 mux, whose inputs are I0,I1 and select line S, the out put is given by the following boolean expression:
Out = S’ I0 + S I1
The AND-OR Implementation (AOI) is shown below:


(b) The NAND gate implementation is:

Answer:



To get B’, we need an extra 2:1 Mux, as inverter. Similarly NAND, NOR, XNOR gates can also be implemented. All these implementations need 2 2:1 Muxes (similarly to XOR gate).

Answer:
Y = A’B’C + A’BC’ + AB’C’ + ABC = A XOR B XOR C

Answer:
Y = A’B’C + A’BC’ + AB’C’ + ABC = A XOR B XOR C

Answer:

The majority function gives 1 if the input has more number of 1s than zeros. The truth table is shown in Chapter 3. If A=B=0, the output will be zero irrespective of C. If A=B=1, output is 1 irrespective of C. But if A=1,B=0 or A=0,B=1, as we can not decide the majority without knowing C. So I0 = 0, I1=I2 = C and I3 =1. The implementation is shown above. If we simplify the expression it gives,
Y = AB+ BC + AC

Answer:
Shannon’s expansion theorem is highly useful in implementing a Boolean function using Multiplexer.
(a) To get f(x,y,z) = x’z’ + xy + xz in terms of x, first use Shannon’s expansion theorem to get the following co-factors. The cofactors are:
f_x = f(1,y,z) = y + z
f_x’ = f(0,y,z) = z’
So, f(x,y,z) = x f_x + x’ f_x’


(b) Now we can use x as select line and implement f(x,y,z) using 2:1 mux

Answer:
We need a 8:1 Mux at the input side and 1:8 Demux at the receiver side. We may need an 8 bit counter which runs at the same clock speed on both the sides to select one of the user.

Answer:
A 2:4 decoder will have 4 O/Ps which are the minterms of the 2 inputs : AB, AB’, A’B, A’B’. Out of the four outputs that are needed, AB and (A+B)’ = A’B’ are directly available. Whereas A+B can be obtained using the extra 2 input OR gate (which is given).
So only O/P that is needed is (AB)’.
(AB)’ = A’ + B’ = A’(B+B’) + B’(A+A’) = A’B + AB’ + A’B’.
So use 3-input OR gate to obtain (AB)’. The whole design is shown below.

Answer:

Answer:
From the above truth table (A9(b)), we can derive the following equations for barrow and difference:
Borrow = Bout = A’B
Difference = Diff = A XOR B

The same equations can be shown using basic gates. (XOR, NOT, AND)

Answer:
The HA equations are, Cout = AB and Sum = A XOR B = AB’ + A’B
Sum XOR Cout = Sum’ Cout + Cout’ Sum
= (AB+A’B’) AB + (A’+B’) (A’B+AB’)
= AB + A’B + AB’ = A + B
So to get OR gate we need two HA. The Sum and Cout of fist HA are given as inputs to second HA. The Sum of second HA gives the A OR B.

Answer:
Sum = A XOR B XOR C and Carry = AB + BC + AC
Full adder from 2 HA and one OR gate:

Answer:
Sum = A XOR B XOR C and Carry = AB + BC + AC

Answer:
The suitable equations are:
Sum = (A XOR B) XOR C
Cout = AB + (A XOR B) C
The implementation is as follows:

Answer:
Two possible implementations of an adder are (a) Ripple carry adder and (b) Carry Look Ahead adder.
(a) The ripple carry adder for adding two 4 bit numbers, A and B is shown below:

S3-S0 indicates the final result and Cout is the final carry.


(b) Carry Look Ahead (CLA)
From the figure that is shown (A14), we can derive the following intermediate equations:

P_i = A_i XOR B_i and G_i = A_i AND B_i ------------------- (1)
Now, Sum = P_i
XOR C_i
and C_i+1 = G_i+ P_iC_i ----------------------------- (2)

Using this equation for carry, we can generate the following algorithm for carry look ahead:
C₀ = Input carry
C₁ = G₀+ P₀C₀
C₂ = G₁+ P₁C₁ = G₁+ P₁(G₀+ P₀C₀) and so on..------------------(3)

By using these recursive equations, we can look a head and decide the carrier, unlike in case of ripple carry adder.
So the three steps involved in CLA adder are:
Step1: Generation of P_i and G_i from A_i and B_i using Eq(1)
Step2: Generation of carrys using Eq(3)
Step3: Finally getting the Sum from P_i and C_i using Eq(2)

Answer:
In ripple carry adder, the carry propagates from first adder to last. As it has to pass through all the adders, the delay in getting the final output is considerably high. Where as it is hard-ware efficient. The scheme for CLA is explained in the previous question. The major advantage of CLA is faster output. But it needs more hardware.

Answer:
To perform the delay calculations, use the circuits that are shown in above answers.
(a) For full adder the best implementation is shown in A14.
XOR gate delay = 10ns and AND/OR gate delay = 5ns
The delay for each adder = 10 + 10 + 5 = 25ns.
For adding 4-bits, we need 4 such adders, so overall delay = 100ns

(b) For CLA, as explained in A15, we need 3 main steps:
Step1: Generation of Pi, Gi: The XOR gate delay = 10ns
Step2: Generation of carry: And-Or stage = 5ns + 5ns = 10ns
Step3: Sum generation: One more XOR operation = 10ns
So the overall delay = 30ns

Answer:
The carry out of a full adder is equivalent to Majority function.
Majority function, Y = Cout = AB + BC + AC

Answer:
The truth table for full subtractor is shown below:

Answer:
F0 + F1 generates 4 carries, FF+FF and FF+F1 generates 8 carries. Whichever generates less number of carries, that one will give the fastest output. So F0+F1 gives fastest output.

Answer:
Case1: Unsigned Numbers:
In N-bits, we can represent numbers from 0 to (2^N) - 1. Suppose if we are adding 2 N bit unsigned numbers and if the result is greater than (2^N) - 1 , overflow will occur. To detect this, check whether the MSB addition (Nth bit) + Carry generated from (N-1) bit addition is generating any carry or not. If there is carry out, there is overflow.

Case2: Signed Numbers:
In N-bits, we can represent numbers from -(2^(N-1)) to (2^(N-1)) - 1. Suppose if we are adding 2 N bit signed numbers and if the result is not in the above range, overflow will occur. To detect overflow in this case:
• The sum of two positive numbers is negative;
• The sum of two negative numbers is positive;
• Subtracting a positive number from a negative one yields a positive result; or
• Subtracting a negative number from a positive one yields a negative result.

Answer:
Y = 3A = 2A + A. The 4-bit binary adder which is shown in A15 (a) can be used as a block box here. As 2A can be obtained by simple right shift operation, one binary adder is sufficient for the complete design.

Answer:
Note that A-B = A + (-B). That is, to subtract B from A, just find the 2’s of B and add that to A. If A > B, the comparator gives 1 at A>B and zero at rest of the outputs. That 1 is used as one of the inputs to the XOR gate, to find the 2’s compliment of B. Similarly, in case of A < B or A = B, we need to find 2’s compliment of A. The complete design is shown below:

Answer:
This is very much similar to the above design. The extra feature is the indication of overflow, which we can get from XOR of the carries C2 and C3.



Overflow = 1 indicates that overflow has occurred. (Refer to A21) And the other logic for finding the 2’s compliment is exactly same as A24.

Answer:
Absolute value of a number is defined as
|A| = A if A>0,
= -A otherwise
We can use the above designed adder/subtractor unit to accomplish this task. The MSB of A, which will be 1 if A is negative, can be used as C.

Answer:

9’s compliment of a BCD number d is given by 9-d. That is just find the 2’s compliment of d and add that to 9. Cout is needed. Just the S3-S0 of the binary adder, shown in the above figure, gives the required result.

Answer:
The BCD addition is explained in Chapter1. If the result is above 9, it is needed to add 6 to obtain the result in BCD number system. So we need two 4-bit binary adders: One is just to add the two BCD numbers. The second one is for adding 6 or 0 to the result. Extra combination logic is needed to identify the overflow. The condition for detecting the overflow can be derived as,
K = Cout + S3 S2 + S3 S1
K = 1 indicates the overflow and addition of 6 is needed. The complete design is shown below:

Answer:
The binary number that is formed from the Carry out as MSB and Sum as LSB, gives the number of 1s of input. The same thing is illustrated in the following table. The sixth column shows Cout-Sum together where as the last column shows the actually number of 1s in the input. Note that both are exactly same.

Answer:
(a) The circuit works as frequency doubler. That is, it gives double the frequency at the output. But the duty cycle depends upon the delay of the gates.

Answer:
Encoder functionality is opposite of a decoder. The output of an encoder corresponds to the binary code of the input. There is a chance that, in the input stream, more than one 1 may present. In that case, to avoid clash, we need to provide the priority to any one of the bits. Here the truth table for priority encoder which gives, highest priority to its LSB, is shown:

Answer:
The simple design using XOR gate is shown below. (Similar to A29)

Answer:
For finding out whether two signals are equal or not, the best logical gate is XOR. The design is shown below. OUT =1 implies that the two binary numbers are not equal.

Answer:
The decoder gives all the possible minterms at the output. We need to just OR all the corresponding minterms to get a particular Boolean functions. If a Boolean function has more minterms which are 1, then take all the minterms which are zero and use NOR gate. Here in case (a) we can directly use OR gate. But case (b), NOR gate is to be used to get the optimal solution.

Answer:
The major applications of flip-flops are:

Data storage

Data transfer

Counting and

Frequency division

Answer:
The differences between a LATCH and a FLIP-FLOP are:

Latch is a level sensitive device where as flip-flop is edge sensitive

Latch is sensitive to glitches on enable pin and flip-flop is immune to glitches

Latches take less gates(also less power) than flip-flops

Latches are faster than flip-flops.

Answer:
D-Latch is called transparent Latch. As it transfers the data as it is to the output on enable.

Answer:
S-R Latch with clock using 2-input NAND gates is shown below:

Answer:
(a) S=R=0
(b) S=R=1

Answer:
Transparent latch from S-R Latch:

Answer:
D-Latch using 2:1 Mux:

Answer:
2 D-latches and an inverter are needed to get the master-slave configuration. The major advantage of master-slave configuration is avoiding the race-around condition as the input changes only at the edges.

Answer:
The race around condition means: the output oscillating between 0s & 1s. This problem will occur in Latches especially if the clock is high for long time. In case of J-K Latch, J=K=1 gives Q(t+1) = Q(t)' . Consider the case when clock is high for long time and J=K=1. Then the output oscillates between 0 & 1 continuously as long as the clock is high. To avoid this, use Master-Slave configuration which latches the input only at clock edges. So in that case, irrespective of the duration of clock high, output will be just compliment of previous output. There won’t be any oscillation as such.

Answer:
The sensor will give 1 for Black and 0 for white. First we will draw the outputs of the sensors assuming some position of the wheel. Assume that the initial position of the wheel is as shown in the figure with respect to the sensors. The output waveforms of S1 and S2 will be as follows. Both clock wise and counter clock wise wave forms are shown here. It is clear from the waveforms that there is an initial delay of 22 ½ degrees between the two waveforms (assuming the two sensors are at the same distance from the partition).

Initially S2 = 0 and S1 =1 because of their initial positions(this is just our assumption). Once the wheel started moving in anti-clock wise direction, S1 will go to 0 from 1 after 22 ½ degrees. And then gets complemented once in 180 degrees. In this case, S2 will go to 0 to 1 after (180 -22 ½ ) degrees and then complements once in 180 degrees.

Similarly we can analyze for clock-wise case also. The waveforms for both the cases are shown below.
(a) For Clock-wise case the waveforms are:

(b) For anti-clock wise, the waveforms are:

These two wave forms are connected to DFF as shown in the following figure. That is S1 to the clock and S2 to the D input.


If you observe the above waveforms, for clock-wise direction, whenever there is a rising edge of S1, S2 is always 0. For anti-clock wise direction, at the rising edge of S1, S2 is 1 always.

That is OUT =1 in the above circuit indicates the clock-wise rotation and OUT = 0 indicates anti-clockwise rotation.

Answer:
The characteristic table for J-K flip flop is:

To get the characteristic equation, we can use K-Map with 3 inputs, J,K and Q(t) and obtain,
Q(t+1) = J Q(t)’ + K’ Q(t)

Answer:
The complete design is shown here. The catch here is to use Q as select line. You can observe the cofactors of Q(t+1) with respect to J,K and Q(t). Using J or K as the select line with 2:1 mux will not do.

Answer:
T-flip flop using DFF:

Answer:
T-flip flop using DFF:

Answer:
During the design process we usually know the transition from present state to the next state and wish to find the flip-flop input conditions that will cause the required transition. For this reason we will need a table that lists the required inputs for a given change of state. Such a list is called the excitation table.

Answer:
The excitation table for T flip flop is shown below.

Answer:
Synchronous reset will clear output only at clock edge unlike asynchronous reset. At clock edge, if syn_rst = 0, output will be 0 otherwise output will be D. So we just need an AND gate before the DFF as shown in the figure.

Answer:
As DFF transmits the data as it is to the output, it can be used to provide one clock delay.

Answer:
In TFF, if T=1, output just toggles between 1 and 0. So TFF can be used as toggle switch.

Answer:
From the given characteristic table, it is clear that if X=0, Q(t+1) = Y XNOR Z. If X =1 and if (Y XNOR Z), Q(t+1) = Q(t), else Q(t)’. So we need two 2:1 mux to generate Y XNOR Z. One to select Q(t) and Q(t)’ and one more to select between X=0 case and X=1 case. Total we need 4 2:1 mux. The design is shown here except the generation of Z’.

Answer:

Answer:

Answer:
To get D from flip-flop from AB flop, just connect A=B=D.
We can prove this from the characteristic equation ,
Q(t+1) = D Q(t)’ + D Q(t) = D (1) = D

Answer:
For NOR based S-R Latch, there is no change in output for S=R=0, 0 for S=1,R=0 and 1 for S=0 and R=1. The waveforms are drawn using this. (Delay of NOR gate = 10ns). Assume that initially Q = 0 and so Q’ = 1.

Answer:

Answer:

Answer:
State Machine for Serial 2’s complementer:
Logic: Starting from LSB, retain all the bits till first one has occurred including the first one and then complement all the following bits.

State Definition:
         State a : No one has occurred
         State b : After first one has occurred

State Diagram:

Answer:
(a) INPUT Sequence : 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1
OUTPUT Sequence : 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1

(b) Note that the OUTPUT is 1 if the input (that has arrived till now) contains odd
number of 1’s. So the FSM shows the functionality of serial odd parity indicator.

(c) The state table is as follows:



The state table shows that NS = OUTPUT = PS XOR INPUT
This is same as the characteristic equation of T- Flip flop.

Answer:
State transition diagram for J-K Flip-flop:
The first bit of the two bits is J and the other is for K.

Answer:
A(t+1) = x’A + xB
B(t+1) = xA’ + x’B


(c) Functionality:

This circuit works as enable based gray code counter. If X=1, the transition takes place in gray code counter and if X=0, there won’t be any change in the present state.

Answer:
One of the possible FSMs is shown below:

Answer:
A state machine consists of set of states, initial state, input symbols and transition function that maps input symbols and current state to next state.

Mealy machine: machines having outputs associated with transition of input and the current state. So Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.

Moore machine: machines having outputs associated with only states, that is the outputs are the properties of states themselves. The output will vary only after the states are varied. So the changes in the output will be only during clock transitions and the outputs are held until you go to some other state.

Advantages and Disadvantages: In Mealy as the output variable is a function of both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output is dependent on only states and not the input signal level.

Answer:
State Machine for detecting “1010”:
Logic: Check for the bit pattern 1010. The end “10” has to be reused for next pattern.
State Definition:
State a : No 1 detected state
State b : One 1 detected state
State c : 10 detected state
State d : 101 detected state

State Diagram:

Answer:
State Machine for detecting “1010”:
Logic: Check for the bit pattern 1010. The end “10” can’t be reused. So after detection of one pattern, just go to initial state. (Here it is State a).
State Definition:
State a : No 1 detected state
State b : One 1 detected state
State c : 10 detected state
State d : 101 detected state

State Diagram:

Answer:
State Machine for detecting “0110”:
Logic: Check for the bit pattern 0110. The end “0” can’t be reused. So after detection of one pattern, just go to initial state. (Here it is State a). That is non overlapping case.
State Definition:
State a : No 0 detected state
State b : atleast One 0 detected state
State c : 01 detected state
State d : 011 detected state

State Diagram:

Answer:
State Machine for detecting “111”:
Logic: If we represent Head with logic 1 and tail with logic 0, Checking for 3 consecutive heads is nothing but pattern matching for “111” (overlapping)
State Definition:
State a : No 1 detected state
State b : One 1 detected state
State c : More than Two 1’s detected state

State Diagram:

Answer:
To remove a state, we need to have another state with the same next state values and output values. If we observe the given state table, state g has all entries same as those of state a. So state g can be replaced with a everywhere. Once g is replaced with a, all the entries of f are same as those of c. Thus, replacing f with c, makes state d same as state b. So with all these changes the reduced state table is shown below:

Answer:

Answer:
State Machine for detecting more than one 1 in last 3 samples:
Logic: Check for the patterns 011, 101, 110 or 111. These 4 patterns have more than one 1.

State Definition: State a : No 1 detected state, continuous 0s State b : One 1 detected state, “01” or “1” detected state State c : Atleast two 1s detected state, “011” or “111” detected state State d : “010” or “001” detected state

Answer:
State Machine for detecting “101” in last 4 samples:
Logic: Possible patterns are: 0101,1101,1010,1011 (overlapping)

State Definition:
State a : Continuous 0s
State b : Atleast one 1, that is “01” or “111….”
State c : 010 detected state
State d : 0101 or 1101 detected state
State Diagram:

Answer:
State Machine for detecting “101” in last 4 samples:
Logic: Check for the patterns 101 or 010 in last 3 samples.

State Definition:
State a : State a : No 1 detected state, continuous 0s
State b : One 1 detected state, “01” or “1” detected state
State c : “10” detected state
State d : continuous 1’s detected state
State Diagram:

Answer:
State Machine for eliminating short length pulses:
Logic: The 1 after two successive 0’s will be made 0. Similarly the zero after two successive 1’s will be made 1. If you are continuous 1s state, minimum 2 0’s zeros are needed to switch to continuous 0s state and vice versa.

State Definition:
State a : Continuous 0s
State b : One 1 in between 0s
State c : Continuous 1s
State d : One 0 in between 1s
State Diagram:

Answer:
One-Hot encoding of FSM uses one flip-flop per state. Only one flip-flop is allowed to have 'logic 1' at anytime. For example, for a five state FSM, the states are "00001", "00010", "00100", "01000", "10000". All other states are illegal. One-Hot encoding trades combinational logic for flip-flops. One hot reduces the next state and output logic complexity. Its good for 'flip-flop' rich implementation technologies. Because the combinational logic is reduced, the length of the critical path can be reduced resulting in a faster FSM. Speed increase is more significant for larger finite state machines. The disadvantage is we end up in using more number of flops.

Answer:
Johnson’s method: 000,001,011,111,110,100

Answer:
(a) Log₂N
(b) Log₂N
(c) N
(d) N/2

Answer:
State Machine for identifying whther the 1’s and 0’s are even or odd:

Logic: The only 4 possibilities are even-even, even-odd, odd-even, odd-odd. So initial state will be even-even as no 1 or no 0. Now if 1 comes it will be even 0s odd 1. Similarly if 0 comes it will be odd 0’s even 1’s. So the state transition will take place accordingly.

State Definition:
State a : Even 0’s Even 1’s
State b : Even 0’s Odd 1’s
State c : Odd 0’s Even 1’s
State d : Odd 0’s Odd 1’s

Outputs:
In state a, outputs are: A = 1, B = 0, C = 0, D=0.
In state b, outputs are: A = 0, B = 1, C = 0, D=0.
In state c, outputs are: A = 0, B = 0, C = 1, D=0.
In state d, outputs are: A = 0, B = 0, C = 0, D=1.

State Diagram:

Answer:
One hot method.
a : 1000, b : 0100, c : 0010, d : 0001
These values are nothing but the four outputs that are needed. So it reduces the output logic complexity.

Answer:
State Machine to detect whether the serial binary number is divisible by 5 or not:

Logic: From the given example we can notice that the data is coming from MSB side. And the possible reminders are 0,1,2,3,4. So we need to have five states each for value and output is made 1 if we reach state ‘a’, reminder 0 state.

State Definition:
State a : Reminder 0
State b : Reminder 1
State c : Reminder 2
State d : Reminder 3
State e : Reminder 4

State Diagram:

Answer:
State Machine to check whether the two inputs have same value for last 3 samples:

Logic: As there are two inputs, at each state we will have four possible transitions based on the two input combinations. If P=Q=1 or P=Q=0 go to next state, otherwise go back to initial state.

State Definition:
State a : P is not equal to Q
State b : P=Q for last 1 sample
State c : P=Q for Atleast last 2 samples

State Diagram:
Out of the two bits that are shown on the arrows, first 1 is for input A and second one is for input B.

Answer:
State Machine with two inputs- Number of 1’s together multiples of 4:

Logic: As there are two inputs, at each state we will have four possible transitions based on the two input combinations. Just count the number of 1’s in X and Y together and check for the reminder if that number is divided by 4. The possible reminders are 0,1,2,3. The output will be 1 if the reminder is 0.

State Definition:
State a : Reminder 0
State b : Reminder 1
State c : Reminder 2
State d : Reminder 3

State Diagram:
Out of the two bits that are shown on the arrows, first 1 is for input A and second one is for input B.

Answer:
State Machine with two inputs:

Logic: As there are two inputs, at each state we will have four possible transitions based on the two input combinations. The output will be one for the first time, if A has same value in the last two clock ticks. After that, output can be made 1 either by condition A or condition B. S for initial transitions B will be don’t care. But once output is 1, that if you are in state d or e, as long as B is 1, the transition will be between d and e only and the output is also 1.

State Definition:
State a : Initial state
State b : A is 0 once (B can be either 1 or 0)
State c : A is 1 once (B can be either 1 or 0)
State d : A has same value for last two samples and it is equal to logic 0
State e : A has same value for last two samples and it is equal to logic 1

State Diagram: Out of the two bits that are shown on the arrows, first 1 is for inp

Answer:
State Machine with two inputs:

a

Answer:

(a) Setup time: Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data is reliably sampled by the clock.

(b) Hold time: The hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data is reliably sampled by the clock.

(c) Clock to Q delay: The clock to Q delay is the amount of the propagation time required for the data signal to reach the output (Q) of the flip flop after the clock event.

Answer:
For a single flip flop, lesser the clock-to-Q delay, more the operating frequency. However, the maximum frequency of operation may be limited by the configuration in which the flip flop is connected. This will be clear in the later parts of the chapter.
Among the 3 flops, the first one, FF1 has less clock to Q delay. So it can operate at maximum frequency which is given by 1/5ns = 200MHz

Answer:
After the posedge of the clock, the output will change after a delay of Tcq. The input of the flop will change after further delay of “dly”. It should be available before the Tsu of the flop.
So the T >= Tcq + Tsu + dly. The same thing is illustrated in the following waveform.

Answer:
For FF1, Tsu + Tcq = 3 + 5 = 8ns
For FF2, Tsu + Tcq = 6 + 4 = 10ns
For FF3, Tsu + Tcq = 8 + 2 = 10ns
As dly = 0, Tsu + Tcq <= T
(a) T = 5ns, None of the flip flops has Tsu + Tcq <= T, so no one can be used.
(b) T = 8ns, FF1 can be used
(c) T = 15ns, Anyone can be used

Answer:



Using the same equation , T >= Tcq + Tsu, T >= 6 + 10. So T >= 16ns.
The maximum clock frequency = 1/16ns = 62.5MHz

Answer:
There are no hold violations in the above circuit. If the hold time is greater than the propagation delay then there will be hold violation for the above circuit. In that case, buffers (even number of inverters) will be used in the feedback path in order to delay the signal in reaching back to the input.

Answer:
(a) Thold <= Tcq + dly. But here, 2ns > 1.5 + 0.5 = 1.7ns. So there is a hold violation in the above circuit.
(b) dly >= Thold – Tcq = 2 – 1.5 = 0.5ns
(c) The delay of the clock buffer will not effect the maximum frequency of operation of the circuit.

Answer:
Clock-skew: Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This is typically due to two causes:

1. The first is a material flaw, which causes a signal to travel faster or slower than expected.
2. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times.

Skew is only meaningful between adjacent pairs of registers, not between any pair of registers in a clock domain.

Answer:
Yes, Hold time of a flip flop can be negative. Most of the modern flip flops will have either 0 or negative hold time. Assume Thold = -2ns, there should not be any transitions in the input before 2ns of the clock event.

Answer:
For the given circuit, T >= Tcq1 + Tsu2.
To get maximum frequency T should be less. So we should select the first flop with less clock to Q delay and second flip flop with less setup time. So FF1 and FF3 give the maximum frequency and it is equal to 1/7ns = 142.8MHz

Answer:

The above waveforms show the CLK, CLK1 and CLK2. The input waveform at FF1 is assumed and the input of FF2 is shown accordingly with all the given delays and clockto-Q delays. From the waveforms it is clear that, to avoid setup time violation,
T >= (Tsu2 + Tcq1 + dly1 – delta) where delta = dly2-dly3 (assuming +ve skew) From this equation we can get maximum freq of operation. To avoid hold time violation,
Th2 <= Tcq1 + dly1 – delta

These two equations can be used as generalized equations to solve setup time/hold time problems. This works only for synch circuits. If one clock works at pos edge and other is negative edge we need to derive one more set of equations. That also we will at later section.

Answer:
(a) There is a hold time violation in the circuit, because of the feedback. Tcq2 +AND gate delay is less than thold2. To avoid this , we need to use even number of inverters(buffers). Here we need to use 2 inverters each with a delay of 1ns. Then the hold time value exactly meets.

(b) In this diagram,
dly3 = 0
dly2 = 2ns
so,delta = 2ns
tsu2 = 3ns, tcq1 = 2ns, dly1 = 5ns

Putting all these values in Eq(1) ,
T >= Tcq1 + dly1 + Tsu2 - delta
so, T >= 2 + 5 + 3 - 2, T >= 8ns, f <= 1/8
Max freq of operation is 125MHz

Answer:
Tcq1 = Tcq2 = 2.5ns
Tsu1 = Tsu2 = 2ns
Thold1 = Thold2 = 1ns
delta = clock_skew = 3 - 0.5 = 2.5ns

Equation for hold-violation is,
Thold <= dly + Tcq1 - delta (Eq(2))
1 <= dly + 2.5 - 2.5
So dly >= 1ns
To obtain maximum freq, fixing it to lowest possible value, so dly = 1ns

Using this value and Eqauation (1) of setup time, we can obtain max freq.
T >= Tcq1 + dly +Tsu2 - delta
T >= 2.5 + 1 + 2 - 2.5
So T >= 3ns Max freq of operation = 1/3ns = 333.33 MHz

Answer:
Setup time:
(T/2) + delta >= Tcq1 + dly1 + Tsu2

Hold time:
Th2 <= delta + Tcq1 + dly1

where delta = dly3 - dly2, assuming positive skewand T is clock period.

Note: The procedure is same as that of Q11.Just draw the waveforms with proper delays, you will get above equations.

Answer:
For FF1 and FF2, T1 >= (Tsu2 + Tcq1 + dly1 – skew1)
For FF2 and FF3, T2 >= (Tsu3 + Tcq2 + dly2 – skew2)
T >= MAX (T1,T2)

Answer:
Metastable state: A un-known state in between the two known logical states is called as Metastable state.

Reason for occurrence: This will happen if the output node capacitance is not allowed to charge/discharge fully to the required logical levels. In case of flip flops, if the input changes in the restricted region, that is if there is a setup time or hold time violations, metastability will occur.

Way to avoid: To avoid this, a series of FFs is used (normally 2 or 3) which will remove the intermediate states. The extra flip flop is called the synchronizer.

Answer:
Given: Tsu = 2ns, Th = -3ns and Tcq = 5ns.
If hold time is negative and if its absolute value is less than Tsu, only thesetup violation equation without any modification will work. But if absolute value of hold time is more than setup time, we need to replace the setup time in the equation with hold time. The modified equation is shown below:
    T >= Tcq1 + dly1 + Max( Tsu2, | Th2 | )
    T >= 5 + dly1 + 3
    T >= 8 + dly1

To get maximum frequency of operation, the minimum possible dly1 = 1ns.
So, T >= 9ns
      Fmax = 1/9ns = 111MHz

Answer:
The shift register is shown below.
If C = 0, the circuit shifts from IN QA -> QB -> QC and
If C = 1, the circuit shifts from IN QC -> QB -> QA

Answer:
Dnext = Q0 xor Q2 xor Q3

Answer:
Ripple counter is asynchronous. This means all flip flop outputs will not change at the same time. The output of one flop works as clock to the next flip flop. The state changes consequently “ripple through” the flip flops, requiring a time proportional to the length of the counter.
          Where as synchronous counters will have same clock for all the flip flops. All flip flops will change the state at the same time. Design of synchronous counters is easy but needs more hardware.
          Although the asynchronous counter is easier to implement, it is more "dangerous" than the synchronous counter. In a complex system, there are many state changes on each clock edge, and some IC's (integrated circuits) respond faster than others. If an external event is allowed to affect a system whenever it occurs, a small percentage of the time it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. What is worse, these problems are difficult to test for and difficult to foresee because of the random time difference between the events.

Answer:
log₂N

Answer:
In the problem it is not clearly mentioned whether

Answer:
The FSM for 3-bit gray counter is shown below. You can notice the single bit change from one state to another state.

Answer:
The FSM for 3-bit gray counter is shown below. You can notice the single bit change from one state to another state.

Answer:
Shift register based: The synchronizer (the first flip flop) aligns the INPUT with clock. The second flip flop delays the input by one clock. Draw the waveforms of output of first and second flip flops and then try to get the relationship between those waveforms and OUT1, OUT2. It gives the complete solution as shown below.

Answer:
Shift register based: Assumed atleast 3 clock gaps between next falling edge. Shift register of width 2 is needed.

Answer:
(a) 50% duty cycle:
Waveforms:.

Design:
(b) 25% duty cycle:
The above circuit gives 50% duty cycle. To get 25%, we need to use an extra AND gate, which takes fin and fout as the inputs.
Waveforms:.

Design:

Answer:
Same as A10(b)

Answer:
Waveforms:

Design:
In the above problem, if you observe the waveforms, they are synchronous. So we can use FSM to design the circuit. If you observe the waveform clearly, output is 100,100,100 and so on. Assume 3 states: a,b & c. Initial state is a and output is 1 in this state. The state transition a -> b -> c -> a. Output is 1 only for state a. The state table is shown below:
PS NS O/P
a   b   1
b   c   0
c   a   0

With State assignment: 00-a,01-b and 10-c, we can obtain the following next state equations:
A(t+1) = B, B(t+1) = A NOR B, OUT = A NOR B

Answer:
(a) Replacing the NOR gate in the above circuit with NAND gate gives a duty cycle of 2/3 ^{. That is 66.67%.
(b) To get 50% duty cycle, by observing the waveforms, we can notice that, an extra flop that works at the negative edge of the clock is needed. ORing of the input and output waveforms of this flip flop gives the required waveform. The complete solution is shown below:}

Answer:
Waveforms:

Design:

Note: The clue to get the solution is: There is a transition at the falling edge of clock. So the clock to the second flop is inverted one. The waveforms shown in the above figure, fout has a duty cycle of 1/3^rd To get 2/3^rd duty cycle, replace NOR gate with NAND gate in the above design.

Answer:
From the given circuit we can derive the following next state equations,
A(t+1) = A’ and B(t+1) = A XOR B’ = AB + A’B’
Taking initial values of A=B=0 and drawing the waveforms with respect to the clock using above equations, we can observe that
OUT = freq_Clock / 4 with duty cycle = 50%

Answer:
The block box can be an up-down counter, where the “count_up_enable” is connected to the sensor at the entrance and “count_down_enable” to the sensor at the exit. That is if there is no one in the room, the counter’s output will be zero. Whenever this happens make the bulb “OFF”.

For 200 people, we need 8 bit counter.
So The O/P of entrance sensor will be used as enable for UP count and the other sensor at exit will be used for DOWN count, whenever the counter's O/P is 0, we can make the BULB OFF, Otherwise ON.

Answer:
Each BCD counter counts from 0-9.

Answer:
Ring counter: A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. This single bit is shifted from one flip flop to the next to produce the sequence of timing signals.

The above circuit shows the ring counter. The initial value of the shift register has to be 1000.

Answer:

Answer:
3-bit counter and 3:8 decoder

Answer:
In “0” passing ring counter, at any time only one flip flop will be set to 0 others will be 1. The given state values are 23 and 29. The binary representations are 10111 and 11101 respectively. So the states are : 01111, 10111,11011,11101,11110. The decimal values are : 15,23,27,29,30.
a = 15, b = 27 and c=30

Answer:
The states of 3-bit Johnson counter are: 000,100,110,111,011,001. So the unused states are 010 and 101

Answer:
2N

Answer:
For N-flops, the total possible states = 2^N.
The number of states of a Johnson counter = 2N
So, the number of unused states = 2^N – 2N

Answer:
The output of last flip flop of a 4-bit counter is equal to the input clock/16.
So output frequency = 160MHz/16 = 10MHz

Answer:
(a) 10 + 10 + 10 + 10 = 40ns
(b) 10ns

Answer:
Minimum time period of the clock = 11 x 40 + 60 = 440+60 = 500 ns So maximum clock frequency = 1/500 = 2 MHz

Answer:
The present state and next state values are shown in the table and the complete design is shown in the following diagram.

Answer:
Let us name the 3 flip flops as A,B and C
Q0 = A’
Q1 = A XOR B
Q2 = (AB) XOR C
Starting with A=B=C=0, the next states can be obtained as:
000 --> 001 --> 010 --> 011 --> 100 --> 101 --> 110 --> 111
So the circuit works as 3-bit binary counter.

Answer:
The output should be asserted 1 if the number of clocks is multiple of 4, that is 0, 4 , 8 and 12. The K-Map simplification gives, OUT = Q1’Q0’ = (Q1 + Q0)’

Answer:


Limitation of the design:
As the design used only one counter, the maximum count is 15.

Answer:
N-bit ring counter gives 1/N times the input frequency at the output. Johnson’s output is 1/2N times the input. Where as the counters output will be 1/(2^N).
F1 = 10MHz / 10 = 1MHz
F2 = 1MHz / 20 = 50KHz
F3 = 50KHz / 16 = 3.125KHz
F4 = 3.125KHz / 8 = 390.625Hz

Answer:
The complete design using shift registers is shown in the following figure. The main clock is gated with the clock enable so that A and B will be shifted just 8 clocks. After 8 clocks A and B will have their contents swapped.

Answer:
A fault in a manufactured circuit causing a node to be stuck at a logical value of 1 (stuck-at-1) or a logic value of 0 (stuck-at-0), independent of the input to the circuit. If any rail during the layout gets connected to either VDD or GND permanently, it will lead to these stuck at problems.

Answer:
Total possible faults are 6. (3 nodes, 2faults for each node) By single fault model, the test patterns that are needed are: 01,10 and 11 The stuck-at-0 problems at any of the inputs and stucl-at-0 problem at the output can not be distinguishable.

Answer:
(a) Test pattern/set : The set of all input combinations that is needed to find out all the stuck-at faults of a digital circuit. Eg: Test set for 2-input AND gate: { 01, 10,11}
(b) ATPG: ATPG, or Automatic test pattern generation is an electronic design automation tool that generates the complete test set to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault.

Answer:
Assume that there is only fault in the given circuit. This is called single fault model. Now apply the input combination such that the correct and faulty circuits would give different outputs.

Answer:
We need to select the pattern such that none of the inputs at AB,C& D should give 0 at any of the inputs of NAND gate. So the possible pattern is: A = B = C = D = 1 So we need to apply 1111 at the input, if it is correct circuit we will get, 0 at the output and if there is stuck-at-0 problem at P, we will get 1 at the output.

Answer:
Single Fault method is used here.

Answer:
N+1

Answer:

Answer:
(a) F = (C+D)’ = C’D’
(b) F = AB

Answer:
If the number of nodes is more in a given circuit, it is very difficult to derive the test pattern by using single fault model (That is analyzing at each node). The other method called “Path sensitized” can be used to make the test pattern generation more efficient. In this method, all the paths from input to the output will be identified and the input will be applied such that the output will be dependant only on one particular path. And this path is called sensitized.

Answer:
• To make F dependant of the high lighted path, the output of XOR gate has to be 1. This can be achieved from A = 0, B = 1 or A = 1, B = 0.
• To make the output of OR gate to make dependant only on one input, the other input has to be 0. This can be achieved either B = 0 or C = 0;
• But C can not fixed to 0. So B has to be 0. That implies A = 1
• To make NOR gate output only C dependant, D has to be 0.
So to make the given path sensitized, the input pattern that is needed is,
A = 1, B = 0, C = 1 or 0 and D = 0

Answer:
(a) 0100 at the input, makes the path A-w1-F sensitized.
So it can be used to detect the following single stuck-at problems:
Stuck-at-1 at A or Stuck-at-0 at w1 or Stuck-at-0 at F’
(b) Path sensitized method is used here.
To make F dependant only on w3, w1 = 0. So A=B=1
Now for identifying the Stuck-at-0 fault at w3, we need to apply input pattern such that we will get 1 at w3.(C=D=1). So the required pattern is 1111.
For identifying the Stuck-at-1 fault, either C or D has to be 0. So any of the following patterns can be used : 1100,1101 or 1110

Answer:

Answer:
(a) The 4-bit even parity generator is shown in the following diagram:

(b) Path sensitized test:

So the complete test set is {0000, 0001, 0010, 01000, 1000}

Answer:
In test of logic circuits, normally the logic levels are represented with D. This is called D-Notation. If Logic-0 is represented with D, logic 1 will be D’ and vice versa.

Answer:
A Static Hazard is defined when a single variable change at the input causes a momentary change in another variable [the output]. A Dynamic Hazard occurs when a change in the input causes multiple changes in the output [i.e. from 1 to 0 and back to 1]. In either case of a Static or Dynamic hazard the product produced is an unanticipated glitch [the hazard]. The resulting glitches in the circuit may or may not induce additional problems, other then increased issues due to switching noise.
   There are two types of Static hazards: the high output transitions to a low and back high [a low going glitch]. Or the low output transitions to a high [1] and back low [0] [a high going glitch]. There are also two types of Dynamic hazards: the 0 output transitions to a 1 back to 0 and then 1 again. Or the 1 output transitions to a 0 back to 1 and then 0 again.

Answer:
(a) ii
(b) i
(c) iii

Answer:
Static-zero Hazard’s characteristics: Two parallel paths for x, one inverted and reconverge at an AND gate.
F = A . A’
Any circuit with a static-0 hazard must reduce to the equivalent circuit of the following figure:

Answer:
Static-one Hazard’s characteristics: Two parallel paths for x, one inverted and reconverge at an OR gate.
F = A + A’
Any circuit with a static-1 hazard must reduce to the equivalent circuit of the following figure:

Answer:
G = AB + A’ C + B’C’D
If B = C = 0, G = A+A’ (Static-0 hazard in A)
If A = 1, C = 0, D = 1, G = B+B’ (Static-0 hazard in B)
If A = 0, D = 1, G = C +C’ (Static-0 hazard in C)

Answer:
To avoid the static hazards, one of the possible ways is delay matching. Suppose in the circuits shown above (A18 & A19), we can provide buffer whose delay is equal to that of NOT gate. But it becomes very difficult to match the delays exactly.
  If Static Hazards are removed from the design, Dynamic Hazards will not occur. A Karnaugh map [K-map] is the easiest way to eliminate a Static Hazard or glitches. A Kmap for each combinatorial logic function which has an output should be used. Redundant prime implicants should be added to the K-Map (circuit), which will guarantee that all single-bit input changes are covered. Multi-level functions will be reduced to "two-level" functions, and analyzed by the K-map approach. The procedure for designing a static-hazard-free network is a straightforward application. The key is to place the function in such a form that the transient output function guarantees that every set of adjacent 1's in the K-map are covered by a term, and that no terms contain both a variable and its complement. The former condition eliminates 1-hazards and the latter eliminates 0-hazards.

Answer:
(b)
The boolean expression, Y = AB + A’C + BC can be further reduced to Y = A’C + AB. But the second expression will have hazards. So the redundant term BC is added. You can observe the K-Map of the same:

Answer:
F(A,B,C,D) = ∑ (0,4,11,13,15) + d(2,3,5,10)
From the K-Map shown below, the simplified expression for F is,
F = ABD + A’C’D’ + B’C
But to make it Hazard free, we need to add the redundant term, ACD to this.
F = ABD + A’C’D’ + ACD (Note that B’C is removed from the equation)

Answer:
The two possible implementations are shown below:

If we compare both the implementations, in implementation (a), the delays from the inputs to the output, F are uniform. So there is no possibility of glitches. Where as in the implementation (b), the delays are not balanced properly. (a) is hazard free and the better implementation when compared to (b).

Answer:
Y = AB + CD

Answer:
CMOS(Complementary MOS) circuits consist of both types of MOS devices interconnected to form logic functions as shown in the following block diagram. The PUN(Pull up network) will charge the output node in case of Logic-1 and the PDN(Pull down network) will discharge by connecting the output node to ground, in this way the out put is connected either to VDD or GND continuously. PUN and PDN are dual logic networks. CMOS take advantage of the fact that both n-channel and p-channel devices be fabricated on the same substrate.

Answer:
The CMOS logic has two important advantages:
Advantages:
• No direct path in steady state between power and ground, so no static power dissipation(except for small power dissipation due to leakage currents)
• Full logic levels (The VTC exhibits a full output voltage swing between 0 and VDD, and that VTC is usually very sharp)
• High noise margins (Good noise immunity)
• Extremely high input resistance; nearly zero steady-state input current
• Low output impedance. Always a path to Vdd or Gnd from output node, in steady state;
• CMOS provides a greater packing density.

Disadvantages:
• CMOS processing is more complex
• Latch up problem
• Slower compared to TTL
• Higher cost

Answer:
(b)

Answer:
CMOS inverter:

Basic operation: When input goes from 0 to 1, the PMOS will be off and the NMOS will be on. This makes the OUT to get connected with GND and goes to 0. Similarly when input is 0, the NMOS will be OFF and PMOS turns ON making the output logic to VDD. We will get full logic levels at the output.

Answer:
Voltage Transfer Characteristics (VTC) of a CMOS inverter:

Answer:
VOH > VIH > VIL > VOL (Refer to VTC shown in A5)

Answer:
(a) Fan_out: The fan-out of a gate specifies the number of standard loads that can be connected to the output of the gate without degrading its normal operation. The fan-out is calculated from the amount of current available in the output of a gate and the amount of current needed in each input of a gate.
Fan_out = Min (I_OH/I_IH, I_OL/I_IL)

(b) Noise margin: Noise margin is the maximum noise voltage that can be added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output.
Noise margin = Min ( V_OH-V_IH, V_IL-V_OL )

Answer:
Given: VOH = 4V, VIH = 3V, VOL = 1V and VIL = 1.5V
VOH – VIH = 4 – 3 = 1
VIL – VOL = 1.5 – 1 = 0.5
Noise Margin = 0.5

Answer:
(a) Fan_out :
IOH = 1mA, IOL = 20mA, IIH = 0.05mA and IIL = 2mA
IOH/IIH = 1/0.05 = 20
IOL/IIL = 20/2 = 10
So, Fan_out = 10

(b) Power dissipation :
VCC = 5V, ICCH = 1mA, ICCL = 2mA
Icc(avg) = ( ICCH + ICCL )/2 = 1.5mA
Power dissipation = VCC * Icc(avg) = 5 * 1.5 = 7.5 mW

Answer:
(b)

Answer:
(a) 2-input NAND gate:

(b) 2-input NOR gate:

Answer:
Deriving the Pull-up network hierarichally identifying sub nets as shown in the following figure:
The complete circuit and the output boolean function is shown below:

Answer:
Deriving the Pull-up network hierarichally identifying sub nets as shown in the following

Answer:
F = ( (A+B) . (C + D))’

Answer:
(a) 4-input NAND gate from 2-input NAND gates:

(b) Number of NMOS = Number of PMOS transistors = 4 (So total, 8)

Answer:
S = A XOR B XOR C and Cout = AB + BC + AC = AB + (A+B)C
S can be rewritten as, S = ABC + (A+B+C) Cout’
For Cout, NMOS = PMOS = 6 (Total 12)
For S, NMOS = PMOS = 8 ( Total 16)
So for one bit full adder implementation, minimum number of transistors that are required = 28

Answer:
The late coming signals are to be placed closer to the output node ie A should go to the NMOS that is closer to the output.
Reason is, by the time A comes, B would have turned on the bottom transistor and discharged the intermediate node between the 2 series NMOS. So by the time A comes, it can discharge the output node very quickly.

Answer:
(d)

Answer:
Stick diagram for CMOS inverter

Answer:
Stick diagram for NOR gate

Answer:
Pass transistor logic:
• A pass transistor is a MOSFET in which an input is applied not only to the gate but also to the drain
• Unlike static CMOS, there is no need for any static power supplies
• More advantageous in terms of number of transistors if the inputs and their complements are available
• Disadvantage is : Degarded logic level as NMOS passes weak logic-1

Answer:
The AND gate using pass transistor logic is shown below:

Answer:
(a) 2:1 Mux
(b) OUT = S I1 + S’ I0
(c) Pass transistor logic
(d) Degraded logic 1. To avoid we need to use both NMOS and PMOS together ( That is transmission gate)

Answer:
Tranmission gate consists of one n-channel and one p-channel MOS transistor connected in parallel. The same thing is shown in the following diagram. When N is at VDD and P is at ground, both transistors conduct and there is a closed path between IN and OUT.

Answer:
Using only an NMOS will result in an poor 1. Assume the gate voltage on NMOS is 5V. If we connect Drain to 5V, and the source is initially at 0, NMOS will turn on as long as Vgs >Vth, this means, once the source reaches 4.3V (Assuming Vth=0.7), the NMOS will turn off and there will be no more increase in source voltage. Similarly the opposite happens with PMOS, it doesn't give us a clean 0, but it can give a full 5V. So we use a combination of both NMOS and PMOS so that our signal doesn't get degraded by Vth on either side of VDD and GND.

Answer:
XOR Using TG:
If we observe the truth table of XOR, if A is 1, output is B’ and if A is 0 output is B. Using this, we can implement the following circuit.

To get XNOR, just connect B directly to bottom TG and B’ to the upper TG.

Answer:
D-Latch using TG:

Answer:
The NMOS transmits the same voltage from drain to source, as long as its value is less than 4V. So in the given diagram the output and input of the inverter are same. If we observe theVTC of an inverter, Vout=Vin at Vth = VDD/2 = 2.5V.So if there is no noise floor, the output will settle to 2.5V (This is theoretical analysis). However practically the circuit will oscillate.

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