Due to DPT rules, there is at least 1 week of DRC Clean up activity after PnR/Timing Converges. I think below suggestions are useful in reducing the number of DPT-DRC’s upfront.

The most common type of DPT DRC is called 𝐨𝐝𝐝 𝐜𝐲𝐜𝐥𝐞 𝐯𝐢𝐨𝐥𝐚𝐭𝐢𝐨𝐧 and that can be fixed by:

• 1. Increasing the spacing between the two polygons pair. (𝐭𝐨 𝐦𝐨𝐯𝐞 𝐭𝐡𝐞𝐦 𝐬𝐞𝐩𝐚𝐫𝐚𝐭𝐞 𝐜𝐨𝐥𝐨𝐫𝐞𝐝 𝐦𝐚𝐬𝐤𝐬).
• 2. Making the cycle even by removing one polygon. (𝐛𝐫𝐞𝐚𝐤 𝐭𝐡𝐞 𝐥𝐨𝐨𝐩).
• 3. Dividing one polygon into 2 pieces that involved an odd cycle to assign them in a different color than change it into an even cycle of four. However, we will have to make sure that the two-piece of the polygon must be overlapped to allow for 𝐥𝐢𝐭𝐡𝐨𝐠𝐫𝐚𝐩𝐡𝐢𝐜 rounding & 𝐦𝐢𝐬𝐚𝐥𝐢𝐠𝐧𝐦𝐞𝐧𝐭 and still ends up with a continuous polygon. (which is also called “𝐒𝐭𝐢𝐭𝐜𝐡”).

What’s the first thing you look at after CTS?

skew, latency, timing, routing congestion.

• - I look at number of buffers/inverters tool has added for each clock.
• - If this number is not as per my calculated estimate then I know something is not ok and CTS is messed up.
• - Based on my experiences, I can estimate how to arrive 𝐚𝐭 𝐧𝐮𝐦𝐛𝐞𝐫 𝐨𝐟 𝐜𝐥𝐨𝐜𝐤 buffers 𝐟𝐨𝐫 𝐚 𝐜𝐥𝐨𝐜𝐤 𝐭𝐫𝐞𝐞. Specially for clocks with large sync fanout.
• - A thumb rule to estimate clock buffer is (𝐬𝐲𝐧𝐜_𝐩𝐢𝐧𝐬_of_clk ÷ cts_𝐦𝐚𝐱_𝐟𝐚𝐧𝐨𝐮𝐭 constraints).
• - If we see a major difference in this ratio Vs actual buff or inv added then it should be investigated.

In my above post, I explained few techniques by which we can #analyze the higher latency issue.

here, 𝐈 𝐚𝐦 𝐰𝐫𝐢𝐭𝐢𝐧𝐠 𝐬𝐨𝐦𝐞 𝐚𝐩𝐩𝐫𝐨𝐚𝐜𝐡𝐞𝐬 𝐰𝐡𝐢𝐜𝐡 𝐰𝐢𝐥𝐥 𝐡𝐞𝐥𝐩 𝐭𝐨 #𝐫𝐞𝐝𝐮𝐜𝐞 𝐢𝐭:

1. We can create 𝐬𝐞𝐩𝐚𝐫𝐚𝐭𝐞 𝐬𝐤𝐞𝐰 𝐠𝐫𝐨𝐮𝐩 for the main clock & the clock due to which our main clock is getting pushed.
2. We can add the 𝐛𝐚𝐥𝐚𝐧𝐜𝐞 𝐩𝐨𝐢𝐧𝐭𝐬 to pull the clock.
3. Sometimes we must 𝐞𝐱𝐩𝐥𝐢𝐜𝐢𝐭𝐥𝐲 𝐬𝐭𝐨𝐩 𝐚 𝐜𝐥𝐨𝐜𝐤 (for eg: on input pin of mux) if two asynchronous clocks are coming on to the two input pins of that mux. Proper case analysis values on select pins of mux also guide tool to propagate the intended clock through its output pin.
4. We can 𝐯𝐞𝐫𝐢𝐟𝐲 𝐭𝐡𝐞 𝐩𝐥𝐚𝐜𝐞𝐦𝐞𝐧𝐭 of the clock related logic. Placing the clock cells according to the logical connections always helps in building optimized clock latency.

A timing path which is converging in placement does violates setup time in post-CTS. I am listing down issues I can think of or I faced:

skew, latency, timing, routing congestion.

• - CTS Skew: During placement, clock tree is ideal and based on 80-100ps clock skew assumption, uncertainty is defined. However post CTS, we see the actual skew on those paths which could be more than our assumption we did at placement (150ps-200ps). This ultimately leads to a setup violation in that path.
• - Crosstalk: At placement, we use the global router to check the overall routing congestion. Intuitively, we assume that a placement with less congestion should have less noise. However it doesn’t show the cross-talk noise map. After clock route, cross-talk delay and noise plays a significant role in timing reduction.
• - HVT Inter corner delay: Moreover, we use HVT cells for hold fixing, which inherently have high inter-corner delay. This difference (comparatively lower for LVT/SVT cells) also leads to increase in data path delay, leading to setup violations.

𝐈𝐧 𝐦𝐨𝐬𝐭 𝐨𝐟 𝐭𝐡𝐞 𝐜𝐢𝐫𝐜𝐮𝐢𝐭𝐬 𝐭𝐡𝐚𝐭 𝐚𝐫𝐞 𝐜𝐮𝐫𝐫𝐞𝐧𝐭𝐥𝐲 𝐮𝐬𝐞𝐝, 𝐩𝐨𝐰𝐞𝐫 𝐢𝐬 𝐚 𝐦𝐚𝐣𝐨𝐫 𝐜𝐨𝐧𝐜𝐞𝐫𝐧.
𝐇𝐞𝐫𝐞 𝐚𝐫𝐞 𝐭𝐡𝐞 𝐝𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐭 𝐰𝐚𝐲𝐬 𝐰𝐡𝐢𝐜𝐡 𝐈 𝐮𝐬𝐞𝐝 𝐭𝐨 𝐫𝐞𝐝𝐮𝐜𝐞 𝐩𝐨𝐰𝐞𝐫 𝐝𝐮𝐫𝐢𝐧𝐠 𝐭𝐡𝐞 𝐢𝐦𝐩𝐥𝐞𝐦𝐞𝐧𝐭𝐚𝐭𝐢𝐨𝐧 𝐨𝐟 𝐝𝐞𝐬𝐢𝐠𝐧:

𝐂𝐥𝐨𝐜𝐤 𝐠𝐚𝐭𝐢𝐧𝐠- To save the dynamic switching power, we use multiple clock gates in our clock paths. Clock gates can be introduced in the design both at RTL & implementation (PNR) level. The concept of clock gating aims to stop the clock of those sequential elements whose data are not toggling.

𝐃𝐲𝐧𝐚𝐦𝐢𝐜 𝐯𝐨𝐥𝐭𝐚𝐠𝐞 & 𝐟𝐫𝐞𝐪𝐮𝐞𝐧𝐜𝐲 𝐬𝐜𝐚𝐥𝐢𝐧𝐠- DVFS is a technique where the clock frequency of a design is decreased to allow a corresponding reduction in supply voltage in the design. Since the dynamic power consumption of a design is directly proportional to the square of the voltage, we achieve significant power reduction with this technique.

𝐏𝐨𝐰𝐞𝐫 𝐫𝐞𝐜𝐨𝐯𝐞𝐫𝐲 𝐩𝐨𝐬𝐭-𝐢𝐦𝐩𝐥𝐞𝐦𝐞𝐧𝐭𝐚𝐭𝐢𝐨𝐧- Once the timing of the design is closed, we run power recovery algorithms on our design. These algorithms look for the timing paths having positive setup slack & convert VT/ downsizes the cells in those paths. This helps us to reduce some leakage/ dynamic power of design post-implementation.